%0 Conference Paper %1 conf/vlsid/MenezesKGRKAP03 %A Menezes, Vinod %A Keshav, C. B. %A Gupta, Sushil %A Roopashree, M. %A Krishnan, S. %A Amerasekera, A. %A Palau, G. %B VLSI Design %D 2003 %I IEEE Computer Society %K dblp %P 122-127 %T Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2003.html#MenezesKGRKAP03 %@ 0-7695-1868-0

@inproceedings{conf/vlsid/MenezesKGRKAP03, added-at = {2023-03-24T00:00:00.000+0100}, author = {Menezes, Vinod and Keshav, C. B. and Gupta, Sushil and Roopashree, M. and Krishnan, S. and Amerasekera, A. and Palau, G.}, biburl = {https://www.bibsonomy.org/bibtex/26e41e04071e626cde7ce6ecfbb93b3df/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2003}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183125}, interhash = {8153d60a4f98e7c6903012b1a1f3da94}, intrahash = {6e41e04071e626cde7ce6ecfbb93b3df}, isbn = {0-7695-1868-0}, keywords = {dblp}, pages = {122-127}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:49.000+0200}, title = {Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2003.html#MenezesKGRKAP03}, year = 2003 }