%0 Journal Article %1 avananthalakshmi2014speed %A A.V.AnanthaLakshmi, G.F.Sudha %D 2014 %E Hope, Dr.Martin %J Int. J. on Recent Trends in Engineering and Technology, %K Fourier Fused arithmetic operations_Fast %N 2 %P 15 %T Area and Speed Efficient Reversible Fused Radix-2 FFT Unit using 4:3 Compressor %U http://searchdl.org/public/journals/2014/IJRTET/10/2/1453.pdf %V 10 %X In this paper, it is proposed to design an area and speed efficient reversible fused Radix -2 FFT unit using 4:3 compressor. Radix-2 Reversible FFT unit requires 24-bit and 48 – bit reversible adders, 24 – bit and 48 – bit reversible subtractors and 24x24 reversible multiplier units. In the proposed architecture, the 24-bit adder has been realized as a reversible carry-look-ahead adder using PRT-2 gate. The proposed reversible carry-look- ahead adder is efficient in terms of transistor count, critical path delay and garbage outputs. Reversible subtractor is realized using TR gate with less critical path delay. The 24x24 bit multiplication operation is fragmented to nine parallel reversible 8x8 bit multiplication modules. It is proposed to design a new reversible design of the 24x24 bit multiplier in which the partial products are added using reversible 4:3 compressors which were realized using PRT-2 gates. The proposed multiplier is optimized in terms of critical path delay and garbage outputs. This paper describes three reversible fused operations and applies them to the implementation of Fast Fourier Transform Processors. The fused operations are reversible add-subtract unit, reversible multiply-add unit and reversible multiply-subtract unit. Thus, Reversible Radix-2 FFT butterfly unit is implemented efficiently with the three fused operations. The fused reversible FFT unit using 4:3 compressor operates at a greater speed and consumes lesser amount of logic resource than the discrete implementation.

@article{avananthalakshmi2014speed, abstract = {In this paper, it is proposed to design an area and speed efficient reversible fused Radix -2 FFT unit using 4:3 compressor. Radix-2 Reversible FFT unit requires 24-bit and 48 – bit reversible adders, 24 – bit and 48 – bit reversible subtractors and 24x24 reversible multiplier units. In the proposed architecture, the 24-bit adder has been realized as a reversible carry-look-ahead adder using PRT-2 gate. The proposed reversible carry-look- ahead adder is efficient in terms of transistor count, critical path delay and garbage outputs. Reversible subtractor is realized using TR gate with less critical path delay. The 24x24 bit multiplication operation is fragmented to nine parallel reversible 8x8 bit multiplication modules. It is proposed to design a new reversible design of the 24x24 bit multiplier in which the partial products are added using reversible 4:3 compressors which were realized using PRT-2 gates. The proposed multiplier is optimized in terms of critical path delay and garbage outputs. This paper describes three reversible fused operations and applies them to the implementation of Fast Fourier Transform Processors. The fused operations are reversible add-subtract unit, reversible multiply-add unit and reversible multiply-subtract unit. Thus, Reversible Radix-2 FFT butterfly unit is implemented efficiently with the three fused operations. The fused reversible FFT unit using 4:3 compressor operates at a greater speed and consumes lesser amount of logic resource than the discrete implementation.}, added-at = {2014-02-01T11:39:23.000+0100}, author = {A.V.AnanthaLakshmi, G.F.Sudha}, biburl = {https://www.bibsonomy.org/bibtex/2401b7e4e77585917cec7419569d9e872/idescitation}, editor = {Hope, Dr.Martin}, interhash = {841ab17452e7aeb1cc92b6f6321052ea}, intrahash = {401b7e4e77585917cec7419569d9e872}, journal = {Int. J. on Recent Trends in Engineering and Technology,}, keywords = {Fourier Fused arithmetic operations_Fast}, month = {January}, number = 2, pages = 15, timestamp = {2014-02-01T11:39:23.000+0100}, title = {Area and Speed Efficient Reversible Fused Radix-2 FFT Unit using 4:3 Compressor}, url = {http://searchdl.org/public/journals/2014/IJRTET/10/2/1453.pdf}, volume = 10, year = 2014 }