%0 Journal Article %1 journals/tvlsi/LiangLST04 %A Liang, Jian %A Laffely, Andrew %A Srinivasan, Sriram %A Tessier, Russell %D 2004 %J IEEE Trans. Very Large Scale Integr. Syst. %K %N 7 %P 711-726 %T An architecture and compiler for scalable on-chip communication. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi12.html#LiangLST04 %V 12

@article{journals/tvlsi/LiangLST04, added-at = {2023-12-13T03:08:43.000+0100}, author = {Liang, Jian and Laffely, Andrew and Srinivasan, Sriram and Tessier, Russell}, biburl = {https://www.bibsonomy.org/bibtex/298a7902c6ccb08c5f893b058e828639a/admin}, ee = {https://doi.org/10.1109/TVLSI.2004.830919}, interhash = {88090d2e1ef4bd22fd56649653da24ec}, intrahash = {98a7902c6ccb08c5f893b058e828639a}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {}, number = 7, pages = {711-726}, timestamp = {2023-12-13T03:08:43.000+0100}, title = {An architecture and compiler for scalable on-chip communication.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi12.html#LiangLST04}, volume = 12, year = 2004 }