%0 Journal Article %1 journals/tcad/DingTP98 %A Ding, Chih-Shun %A Tsui, Chi-Ying %A Pedram, Massoud %D 1998 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 11 %P 1099-1107 %T Gate-level power estimation using tagged probabilistic simulation. %U http://dblp.uni-trier.de/db/journals/tcad/tcad17.html#DingTP98 %V 17

@article{journals/tcad/DingTP98, added-at = {2020-09-24T00:00:00.000+0200}, author = {Ding, Chih-Shun and Tsui, Chi-Ying and Pedram, Massoud}, biburl = {https://www.bibsonomy.org/bibtex/206827d8ed12481ca7a3d69a4a8ff80a3/dblp}, ee = {https://doi.org/10.1109/43.736184}, interhash = {89fca2cdebb055bfd5773ad1cede9737}, intrahash = {06827d8ed12481ca7a3d69a4a8ff80a3}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 11, pages = {1099-1107}, timestamp = {2020-09-25T11:48:15.000+0200}, title = {Gate-level power estimation using tagged probabilistic simulation.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad17.html#DingTP98}, volume = 17, year = 1998 }