%0 Conference Paper %1 conf/fpt/QiAC16 %A Qi, He %A Ayorinde, Oluseyi A. %A Calhoun, Benton H. %B FPT %D 2016 %E Song, Yuchen %E Wang, Shaojun %E Nelson, Brent %E Li, Junbao %E Peng, Yu %I IEEE %K dblp %P 20-27 %T An energy-efficient near/sub-threshold FPGA interconnect architecture using dynamic voltage scaling and power-gating. %U http://dblp.uni-trier.de/db/conf/fpt/fpt2016.html#QiAC16 %@ 978-1-5090-5602-6

@inproceedings{conf/fpt/QiAC16, added-at = {2017-05-24T00:00:00.000+0200}, author = {Qi, He and Ayorinde, Oluseyi A. and Calhoun, Benton H.}, biburl = {https://www.bibsonomy.org/bibtex/28fe67adc0806f187fff751080f6118a6/dblp}, booktitle = {FPT}, crossref = {conf/fpt/2016}, editor = {Song, Yuchen and Wang, Shaojun and Nelson, Brent and Li, Junbao and Peng, Yu}, ee = {https://doi.org/10.1109/FPT.2016.7929183}, interhash = {8ae752599c6bea7a9c62669c1fc491d8}, intrahash = {8fe67adc0806f187fff751080f6118a6}, isbn = {978-1-5090-5602-6}, keywords = {dblp}, pages = {20-27}, publisher = {IEEE}, timestamp = {2019-10-17T23:10:51.000+0200}, title = {An energy-efficient near/sub-threshold FPGA interconnect architecture using dynamic voltage scaling and power-gating.}, url = {http://dblp.uni-trier.de/db/conf/fpt/fpt2016.html#QiAC16}, year = 2016 }