%0 Journal Article %1 journals/tvlsi/HwangL12 %A Hwang, Yin-Tsung %A Lin, Jin-Fa %D 2012 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 9 %P 1738-1742 %T Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi20.html#HwangL12 %V 20

@article{journals/tvlsi/HwangL12, added-at = {2020-03-11T00:00:00.000+0100}, author = {Hwang, Yin-Tsung and Lin, Jin-Fa}, biburl = {https://www.bibsonomy.org/bibtex/22901451a0d88589d6efd511e33c21309/dblp}, ee = {https://doi.org/10.1109/TVLSI.2011.2161598}, interhash = {8b1dc93e65086129702118cd2a1c94b8}, intrahash = {2901451a0d88589d6efd511e33c21309}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 9, pages = {1738-1742}, timestamp = {2020-03-12T11:42:31.000+0100}, title = {Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi20.html#HwangL12}, volume = 20, year = 2012 }