Inproceedings,
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.
H. Lee, W. Yun, Y. Choi, H. Choi, J. Lee, K. Kim, S. Kang, J. Yang, J. Kang, H. Lee, D. Lee, S. Sim, Y. Kim, W. Choi, K. Song, S. Shin, H. Moon, S. Kwack, J. Lee, N. Park, K. Kim, Y. Choi, J. Ahn, and B. Chung.ISSCC, page 140-141. IEEE, (2009)
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- conf/isscc/LeeYCCLKKYKLLSKCSSMKLPKCAC09
- entry type
- inproceedings
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- ISSCC
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- 2009
- pages
- 140-141
- publisher
- IEEE
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- conf/isscc/2009
- ee
- http://dx.doi.org/10.1109/ISSCC.2009.4977347
- isbn
- 978-1-4244-3458-9
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- http://dblp.uni-trier.de/db/conf/isscc/isscc2009.html#LeeYCCLKKYKLLSKCSSMKLPKCAC09
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%1 conf/isscc/LeeYCCLKKYKLLSKCSSMKLPKCAC09
%A Lee, Hyun-Woo
%A Yun, Won-Joo
%A Choi, Young-Kyoung
%A Choi, Hyang-Hwa
%A Lee, Jong-Jin
%A Kim, Ki-Han
%A Kang, Shin-Deok
%A Yang, Ji-Yeon
%A Kang, Jae-Suck
%A Lee, Hyeng-Ouk
%A Lee, Dong-Uk
%A Sim, Sujeong
%A Kim, Young-Ju
%A Choi, Won-Jun
%A Song, Keun-Soo
%A Shin, Sang-Hoon
%A Moon, Hyung-Wook
%A Kwack, Seung-Wook
%A Lee, Jung-Woo
%A Park, Nak-Kyu
%A Kim, Kwan-Weon
%A Choi, Young-Jung
%A Ahn, Jin-Hong
%A Chung, Byong-Tae
%B ISSCC
%D 2009
%I IEEE
%K dblp
%P 140-141
%T A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2009.html#LeeYCCLKKYKLLSKCSSMKLPKCAC09
%@ 978-1-4244-3458-9
@inproceedings{conf/isscc/LeeYCCLKKYKLLSKCSSMKLPKCAC09,
added-at = {2015-10-13T00:00:00.000+0200},
author = {Lee, Hyun-Woo and Yun, Won-Joo and Choi, Young-Kyoung and Choi, Hyang-Hwa and Lee, Jong-Jin and Kim, Ki-Han and Kang, Shin-Deok and Yang, Ji-Yeon and Kang, Jae-Suck and Lee, Hyeng-Ouk and Lee, Dong-Uk and Sim, Sujeong and Kim, Young-Ju and Choi, Won-Jun and Song, Keun-Soo and Shin, Sang-Hoon and Moon, Hyung-Wook and Kwack, Seung-Wook and Lee, Jung-Woo and Park, Nak-Kyu and Kim, Kwan-Weon and Choi, Young-Jung and Ahn, Jin-Hong and Chung, Byong-Tae},
biburl = {https://www.bibsonomy.org/bibtex/223c82b5e757ce562adc809f2a92b7f30/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2009},
ee = {http://dx.doi.org/10.1109/ISSCC.2009.4977347},
interhash = {8d2425acd62e27d580df6a307e5f64f7},
intrahash = {23c82b5e757ce562adc809f2a92b7f30},
isbn = {978-1-4244-3458-9},
keywords = {dblp},
pages = {140-141},
publisher = {IEEE},
timestamp = {2015-10-14T11:35:13.000+0200},
title = {A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2009.html#LeeYCCLKKYKLLSKCSSMKLPKCAC09},
year = 2009
}