%0 Conference Paper %1 conf/vlsid/MallyaPR15 %A Mallya, Neethu Bal %A Patil, Geeta %A Raveendran, Biju K. %B VLSID %D 2015 %I IEEE Computer Society %K dblp %P 65-70 %T Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2015.html#MallyaPR15 %@ 978-1-4799-6658-5

@inproceedings{conf/vlsid/MallyaPR15, added-at = {2023-03-24T00:00:00.000+0100}, author = {Mallya, Neethu Bal and Patil, Geeta and Raveendran, Biju K.}, biburl = {https://www.bibsonomy.org/bibtex/241964f76744a3d9b61b4ee0e8c0d9060/dblp}, booktitle = {VLSID}, crossref = {conf/vlsid/2015}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2015.16}, interhash = {93bbe18fa6571f347f4b4be9336ddad0}, intrahash = {41964f76744a3d9b61b4ee0e8c0d9060}, isbn = {978-1-4799-6658-5}, keywords = {dblp}, pages = {65-70}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T01:05:03.000+0200}, title = {Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2015.html#MallyaPR15}, year = 2015 }