%0 Conference Paper %1 conf/vlsid/SureshVKJ05 %A Suresh, B. %A Visvanathan, V. %A Krishnan, R. S. %A Jamadagni, H. S. %B VLSI Design %D 2005 %I IEEE Computer Society %K dblp %P 768-773 %T Application of Alpha Power Law Models to PLL Design Methodology. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2005.html#SureshVKJ05 %@ 0-7695-2264-5

@inproceedings{conf/vlsid/SureshVKJ05, added-at = {2023-03-24T00:00:00.000+0100}, author = {Suresh, B. and Visvanathan, V. and Krishnan, R. S. and Jamadagni, H. S.}, biburl = {https://www.bibsonomy.org/bibtex/27967e66371cb99fa61105025fa178f22/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2005}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2005.54}, interhash = {9559cedd263167867e48490d848beedd}, intrahash = {7967e66371cb99fa61105025fa178f22}, isbn = {0-7695-2264-5}, keywords = {dblp}, pages = {768-773}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:41.000+0200}, title = {Application of Alpha Power Law Models to PLL Design Methodology.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2005.html#SureshVKJ05}, year = 2005 }