%0 Conference Paper %1 conf/isicir/LuoCDYMT14 %A Luo, Junwen %A Coapes, Graeme %A Degenaar, Patrick %A Yamazaki, Tadashi %A Mak, Terrence S. T. %A Tin, Chung %B ISIC %D 2014 %I IEEE %K dblp %P 276-279 %T A real-time silicon cerebellum spiking neural model based on FPGA. %U http://dblp.uni-trier.de/db/conf/isicir/isic2014.html#LuoCDYMT14 %@ 978-1-4799-4833-8

@inproceedings{conf/isicir/LuoCDYMT14, added-at = {2021-10-14T00:00:00.000+0200}, author = {Luo, Junwen and Coapes, Graeme and Degenaar, Patrick and Yamazaki, Tadashi and Mak, Terrence S. T. and Tin, Chung}, biburl = {https://www.bibsonomy.org/bibtex/203ff7ff426f342cd8aa2d4e6953f71e9/dblp}, booktitle = {ISIC}, crossref = {conf/isicir/2014}, ee = {https://www.wikidata.org/entity/Q59334701}, interhash = {95be622dd8db539bc1bc969660262849}, intrahash = {03ff7ff426f342cd8aa2d4e6953f71e9}, isbn = {978-1-4799-4833-8}, keywords = {dblp}, pages = {276-279}, publisher = {IEEE}, timestamp = {2024-04-10T12:19:01.000+0200}, title = {A real-time silicon cerebellum spiking neural model based on FPGA.}, url = {http://dblp.uni-trier.de/db/conf/isicir/isic2014.html#LuoCDYMT14}, year = 2014 }