%0 Conference Paper %1 conf/fpl/NiuNYWYL16 %A Niu, Xinyu %A Ng, Nicholas %A Yuki, Tomofumi %A Wang, Shaojun %A Yoshida, Nobuko %A Luk, Wayne %B FPL %D 2016 %E Ienne, Paolo %E Najjar, Walid A. %E Anderson, Jason Helge %E Brisk, Philip %E Stechele, Walter %I IEEE %K %P 1-4 %T EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2016.html#NiuNYWYL16 %@ 978-2-8399-1844-2

@inproceedings{conf/fpl/NiuNYWYL16, added-at = {2023-12-13T04:55:59.000+0100}, author = {Niu, Xinyu and Ng, Nicholas and Yuki, Tomofumi and Wang, Shaojun and Yoshida, Nobuko and Luk, Wayne}, biburl = {https://www.bibsonomy.org/bibtex/2c6335f573c5afe7ad155fe22c223bbee/admin}, booktitle = {FPL}, crossref = {conf/fpl/2016}, editor = {Ienne, Paolo and Najjar, Walid A. and Anderson, Jason Helge and Brisk, Philip and Stechele, Walter}, ee = {https://doi.org/10.1109/FPL.2016.7577359}, interhash = {9c3a477031d41e7497bac7bcf90c30cb}, intrahash = {c6335f573c5afe7ad155fe22c223bbee}, isbn = {978-2-8399-1844-2}, keywords = {}, pages = {1-4}, publisher = {IEEE}, timestamp = {2023-12-13T04:55:59.000+0100}, title = {EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2016.html#NiuNYWYL16}, year = 2016 }