Article,

Automatic Synthesis and Formal Verification of Interfaces Between Incompatible Soft Intellectual Properties

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ACEEE Int. J. on Information Technology, (March 2013)

Abstract

In this work, we are concerned with automatic synthesis and formal verification of interfaces between incompatible soft intellectual properties (IPs) for System On Chip (SOC) design. IPs Structural and dynamic aspects are modeled via UML2.x diagrams such as structural, timing and Statecharts diagrams. From these diagrams, interfaces are generated automatically between incompatible IPs following an interface synthesis algorithm. Interfaces behaviors verification is performed by the model checker that is integrated in Maude language. A Maude specification including interface specification and properties for verification are generated automatically from UML diagrams.

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