%0 Conference Paper %1 conf/nanoarch/WuCWTSTZ15 %A Wu, Bi %A Cheng, Yuanqing %A Wang, Ying %A Todri-Sanial, Aida %A Sun, Guangyu %A Torres, Lionel %A Zhao, Weisheng %B NANOARCH %D 2015 %I IEEE Computer Society %K %P 7-12 %T An architecture-level cache simulation framework supporting advanced PMA STT-MRAM. %U http://dblp.uni-trier.de/db/conf/nanoarch/nanoarch2015.html#WuCWTSTZ15 %@ 978-1-4673-7849-9

@inproceedings{conf/nanoarch/WuCWTSTZ15, added-at = {2023-12-13T05:25:44.000+0100}, author = {Wu, Bi and Cheng, Yuanqing and Wang, Ying and Todri-Sanial, Aida and Sun, Guangyu and Torres, Lionel and Zhao, Weisheng}, biburl = {https://www.bibsonomy.org/bibtex/22e8b54f78c5cc84fe70bacbafe77f1c4/admin}, booktitle = {NANOARCH}, crossref = {conf/nanoarch/2015}, ee = {http://doi.ieeecomputersociety.org/10.1109/NANOARCH.2015.7180576}, interhash = {a26b3a1532df490021998821f935359e}, intrahash = {2e8b54f78c5cc84fe70bacbafe77f1c4}, isbn = {978-1-4673-7849-9}, keywords = {}, pages = {7-12}, publisher = {IEEE Computer Society}, timestamp = {2023-12-13T05:25:44.000+0100}, title = {An architecture-level cache simulation framework supporting advanced PMA STT-MRAM.}, url = {http://dblp.uni-trier.de/db/conf/nanoarch/nanoarch2015.html#WuCWTSTZ15}, year = 2015 }