%0 Journal Article %1 journals/jssc/Chan0SUM16 %A Chan, Chi-Hang %A Zhu, Yan %A Sin, Sai-Weng %A U, Seng-Pan %A Martins, Rui Paulo %D 2016 %J IEEE J. Solid State Circuits %K dblp %N 2 %P 365-377 %T A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC. %U http://dblp.uni-trier.de/db/journals/jssc/jssc51.html#Chan0SUM16 %V 51

@article{journals/jssc/Chan0SUM16, added-at = {2020-12-29T00:00:00.000+0100}, author = {Chan, Chi-Hang and Zhu, Yan and Sin, Sai-Weng and U, Seng-Pan and Martins, Rui Paulo}, biburl = {https://www.bibsonomy.org/bibtex/223f63c5f8e9188ddf3c851bf29bf0c32/dblp}, ee = {https://doi.org/10.1109/JSSC.2015.2493167}, interhash = {a64000a5d149a7950522015fca5ac2dd}, intrahash = {23f63c5f8e9188ddf3c851bf29bf0c32}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 2, pages = {365-377}, timestamp = {2024-04-08T10:42:20.000+0200}, title = {A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc51.html#Chan0SUM16}, volume = 51, year = 2016 }