%0 Conference Paper %1 conf/islped/ShinKLS13 %A Shin, Insup %A Kim, Jae-Joon %A Lin, Yu-Shiang %A Shin, Youngsoo %B ISLPED %D 2013 %E Chou, Pai H. %E Huang, Ru %E Xie, Yuan %E Karnik, Tanay %I IEEE %K dblp %P 199-204 %T A pipeline architecture with 1-cycle timing error correction for low voltage operations. %U http://dblp.uni-trier.de/db/conf/islped/islped2013.html#ShinKLS13 %@ 978-1-4799-1235-3

@inproceedings{conf/islped/ShinKLS13, added-at = {2015-04-23T00:00:00.000+0200}, author = {Shin, Insup and Kim, Jae-Joon and Lin, Yu-Shiang and Shin, Youngsoo}, biburl = {https://www.bibsonomy.org/bibtex/2d5c731ed5939bc40f0fadfec403cc201/dblp}, booktitle = {ISLPED}, crossref = {conf/islped/2013}, editor = {Chou, Pai H. and Huang, Ru and Xie, Yuan and Karnik, Tanay}, ee = {http://dl.acm.org/citation.cfm?id=2648719}, interhash = {ac963cd57fc7168c6fabf5ab80de752a}, intrahash = {d5c731ed5939bc40f0fadfec403cc201}, isbn = {978-1-4799-1235-3}, keywords = {dblp}, pages = {199-204}, publisher = {IEEE}, timestamp = {2015-04-28T17:09:29.000+0200}, title = {A pipeline architecture with 1-cycle timing error correction for low voltage operations.}, url = {http://dblp.uni-trier.de/db/conf/islped/islped2013.html#ShinKLS13}, year = 2013 }