%0 Conference Paper %1 conf/vlsid/ShahRV12 %A Shah, Jimit %A Raghunandan, K. S. %A Varghese, Kuruvilla %B VLSI Design %D 2012 %E Agrawal, Vishwani D. %E Chakradhar, Srimat T. %I IEEE Computer Society %K dblp %P 107-112 %T HD Resolution Intra Prediction Architecture for H.264 Decoder. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2012.html#ShahRV12 %@ 978-1-4673-0438-2

@inproceedings{conf/vlsid/ShahRV12, added-at = {2023-03-24T00:00:00.000+0100}, author = {Shah, Jimit and Raghunandan, K. S. and Varghese, Kuruvilla}, biburl = {https://www.bibsonomy.org/bibtex/2334223beaef08d62edfd69fcc4444939/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2012}, editor = {Agrawal, Vishwani D. and Chakradhar, Srimat T.}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2012.55}, interhash = {ca04e51526d5741efc455c8ae6f9ce2e}, intrahash = {334223beaef08d62edfd69fcc4444939}, isbn = {978-1-4673-0438-2}, keywords = {dblp}, pages = {107-112}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T01:05:21.000+0200}, title = {HD Resolution Intra Prediction Architecture for H.264 Decoder.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2012.html#ShahRV12}, year = 2012 }