%0 Conference Paper %1 conf/fpl/LiuS16 %A Liu, Dong %A Schäfer, Benjamin Carrión %B FPL %D 2016 %E Ienne, Paolo %E Najjar, Walid A. %E Anderson, Jason Helge %E Brisk, Philip %E Stechele, Walter %I IEEE %K dblp %P 1-8 %T Efficient and reliable High-Level Synthesis Design Space Explorer for FPGAs. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2016.html#LiuS16 %@ 978-2-8399-1844-2

@inproceedings{conf/fpl/LiuS16, added-at = {2020-12-29T00:00:00.000+0100}, author = {Liu, Dong and Schäfer, Benjamin Carrión}, biburl = {https://www.bibsonomy.org/bibtex/2a17b2fba40aea7fb0d07a809ebe3815e/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2016}, editor = {Ienne, Paolo and Najjar, Walid A. and Anderson, Jason Helge and Brisk, Philip and Stechele, Walter}, ee = {https://doi.org/10.1109/FPL.2016.7577370}, interhash = {d049381c6d62012782a2b2e802f991c8}, intrahash = {a17b2fba40aea7fb0d07a809ebe3815e}, isbn = {978-2-8399-1844-2}, keywords = {dblp}, pages = {1-8}, publisher = {IEEE}, timestamp = {2024-04-10T14:52:01.000+0200}, title = {Efficient and reliable High-Level Synthesis Design Space Explorer for FPGAs.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2016.html#LiuS16}, year = 2016 }