%0 Conference Paper %1 conf/socc/ChenLYLH16 %A Chen, Sao-Jie %A Liu, Grace %A Yang, Hsin-Ping %A Luo, Cheng-Hao %A Hwu, Wen-Mei W. %B SoCC %D 2016 %E Bhatia, Karan S. %E Alioto, Massimo %E Zhao, Danella %E Marshall, Andrew %E Sridhar, Ramalingam %I IEEE %K dblp %P 217-222 %T Design of a power-efficient ARM processor with a timing-error detection and correction mechanism. %U http://dblp.uni-trier.de/db/conf/socc/socc2016.html#ChenLYLH16 %@ 978-1-5090-1367-8

@inproceedings{conf/socc/ChenLYLH16, added-at = {2017-11-27T00:00:00.000+0100}, author = {Chen, Sao-Jie and Liu, Grace and Yang, Hsin-Ping and Luo, Cheng-Hao and Hwu, Wen-Mei W.}, biburl = {https://www.bibsonomy.org/bibtex/2bf1c7d65b93d006e39cf3dc73fa3df4a/dblp}, booktitle = {SoCC}, crossref = {conf/socc/2016}, editor = {Bhatia, Karan S. and Alioto, Massimo and Zhao, Danella and Marshall, Andrew and Sridhar, Ramalingam}, ee = {https://doi.org/10.1109/SOCC.2016.7905471}, interhash = {d4f7751a933e5060850e8bac92cb1d2a}, intrahash = {bf1c7d65b93d006e39cf3dc73fa3df4a}, isbn = {978-1-5090-1367-8}, keywords = {dblp}, pages = {217-222}, publisher = {IEEE}, timestamp = {2017-12-08T01:19:57.000+0100}, title = {Design of a power-efficient ARM processor with a timing-error detection and correction mechanism.}, url = {http://dblp.uni-trier.de/db/conf/socc/socc2016.html#ChenLYLH16}, year = 2016 }