Inproceedings,
Robust analytical gate delay modeling for low voltage circuits.
A. Ramalingam, S. Kodakara, A. Devgan, and D. Pan.ASP-DAC, page 61-66. IEEE, (2006)
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- BibTeX key
- conf/aspdac/RamalingamKDP06
- entry type
- inproceedings
- booktitle
- ASP-DAC
- year
- 2006
- pages
- 61-66
- publisher
- IEEE
- crossref
- conf/aspdac/2006
- ee
- https://doi.org/10.1145/1118299.1118315
- isbn
- 0-7803-9451-8
- url
- http://dblp.uni-trier.de/db/conf/aspdac/aspdac2006.html#RamalingamKDP06
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- please select -%0 Conference Paper
%1 conf/aspdac/RamalingamKDP06
%A Ramalingam, Anand
%A Kodakara, Sreekumar V.
%A Devgan, Anirudh
%A Pan, David Z.
%B ASP-DAC
%D 2006
%E Hirose, Fumiyasu
%I IEEE
%K dblp
%P 61-66
%T Robust analytical gate delay modeling for low voltage circuits.
%U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2006.html#RamalingamKDP06
%@ 0-7803-9451-8
@inproceedings{conf/aspdac/RamalingamKDP06,
added-at = {2018-11-06T00:00:00.000+0100},
author = {Ramalingam, Anand and Kodakara, Sreekumar V. and Devgan, Anirudh and Pan, David Z.},
biburl = {https://www.bibsonomy.org/bibtex/2ebaf257fe84c033d47d68c725a889a0b/dblp},
booktitle = {ASP-DAC},
crossref = {conf/aspdac/2006},
editor = {Hirose, Fumiyasu},
ee = {https://doi.org/10.1145/1118299.1118315},
interhash = {d91f2644aae4ad08fd4ae5b49f855a10},
intrahash = {ebaf257fe84c033d47d68c725a889a0b},
isbn = {0-7803-9451-8},
keywords = {dblp},
pages = {61-66},
publisher = {IEEE},
timestamp = {2019-10-17T16:45:43.000+0200},
title = {Robust analytical gate delay modeling for low voltage circuits.},
url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2006.html#RamalingamKDP06},
year = 2006
}