%0 Journal Article %1 journals/tvlsi/SehgalOC06 %A Sehgal, Anuja %A Ozev, Sule %A Chakrabarty, Krishnendu %D 2006 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 3 %P 292-304 %T Test infrastructure design for mixed-signal SOCs with wrapped analog cores. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi14.html#SehgalOC06 %V 14

@article{journals/tvlsi/SehgalOC06, added-at = {2020-03-11T00:00:00.000+0100}, author = {Sehgal, Anuja and Ozev, Sule and Chakrabarty, Krishnendu}, biburl = {https://www.bibsonomy.org/bibtex/2a89631486c9ae0fe88490c8a03ce017e/dblp}, ee = {https://doi.org/10.1109/TVLSI.2006.871758}, interhash = {d9f7cfc9f64e3603bf9965576c5226c0}, intrahash = {a89631486c9ae0fe88490c8a03ce017e}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 3, pages = {292-304}, timestamp = {2020-03-12T11:42:08.000+0100}, title = {Test infrastructure design for mixed-signal SOCs with wrapped analog cores.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi14.html#SehgalOC06}, volume = 14, year = 2006 }