%0 Journal Article %1 V__2015 %A Bhagat, Abhijeet V. %A Sayankar, Bharati B. %A Agrawal, Pankaj %D 2015 %I Auricle Technologies, Pvt., Ltd. %J International Journal on Recent and Innovation Trends in Computing and Communication %K (CS) (PS) (RC) (SA) (ST) (VA) (VCS) Network-on-chip(NoC) allocation channel circuit circuit-switched computation packet-switched route switch traversal virtual %N 2 %P 545--548 %R 10.17762/ijritcc2321-8169.150226 %T Minimization of Latency and Power for Network-on-Chip %U http://dx.doi.org/10.17762/ijritcc2321-8169.150226 %V 3 %X Network-on-chip (NoC) has emerged as a imperative aspect that determines the performance and power consumption of many-core systems. This paper proposes a combination scheme for NoCs, which aims at gaining low latency and low power consumption. In the presented combination scheme, a peculiar switching mechanism, called virtual circuit switching, is proposed to interweave with circuit switching and packet switching. Flits traveling in virtual circuit switching can pass through the router with only one stage. In addition, multiple virtual circuit-switched (VCS) connections are granted to share a common physical channel. Moreover, a path allocation algorithm is used in this paper to determine VCS connections and circuit-switched connections on a mesh-connected NoC, such that both communication latency and power are optimized

@article{V__2015, abstract = {Network-on-chip (NoC) has emerged as a imperative aspect that determines the performance and power consumption of many-core systems. This paper proposes a combination scheme for NoCs, which aims at gaining low latency and low power consumption. In the presented combination scheme, a peculiar switching mechanism, called virtual circuit switching, is proposed to interweave with circuit switching and packet switching. Flits traveling in virtual circuit switching can pass through the router with only one stage. In addition, multiple virtual circuit-switched (VCS) connections are granted to share a common physical channel. Moreover, a path allocation algorithm is used in this paper to determine VCS connections and circuit-switched connections on a mesh-connected NoC, such that both communication latency and power are optimized}, added-at = {2015-08-04T07:16:31.000+0200}, author = {Bhagat, Abhijeet V. and Sayankar, Bharati B. and Agrawal, Pankaj}, biburl = {https://www.bibsonomy.org/bibtex/2ca333db6aa20507915e71efc8208dac8/ijritcc}, doi = {10.17762/ijritcc2321-8169.150226}, interhash = {e2a02b65bbbc827f531e17b8ebbd9b4b}, intrahash = {ca333db6aa20507915e71efc8208dac8}, journal = {International Journal on Recent and Innovation Trends in Computing and Communication}, keywords = {(CS) (PS) (RC) (SA) (ST) (VA) (VCS) Network-on-chip(NoC) allocation channel circuit circuit-switched computation packet-switched route switch traversal virtual}, month = {february}, number = 2, pages = {545--548}, publisher = {Auricle Technologies, Pvt., Ltd.}, timestamp = {2015-08-04T07:16:31.000+0200}, title = {Minimization of Latency and Power for Network-on-Chip}, url = {http://dx.doi.org/10.17762/ijritcc2321-8169.150226}, volume = 3, year = 2015 }