%0 Conference Paper %1 conf/ieeehpcs/YebenesMEGQ16 %A Yebenes, Pedro %A Mathey, German Maglione %A Escudero-Sahuquillo, Jesús %A García, Pedro Javier %A Quiles, Francisco J. %B HPCS %D 2016 %I IEEE %K dblp %P 380-386 %T Modeling a switch architecture with virtual output queues and virtual channels in HPC-systems simulators. %U http://dblp.uni-trier.de/db/conf/ieeehpcs/ieeehpcs2016.html#YebenesMEGQ16 %@ 978-1-5090-2088-1

@inproceedings{conf/ieeehpcs/YebenesMEGQ16, added-at = {2016-09-20T00:00:00.000+0200}, author = {Yebenes, Pedro and Mathey, German Maglione and Escudero-Sahuquillo, Jesús and García, Pedro Javier and Quiles, Francisco J.}, biburl = {https://www.bibsonomy.org/bibtex/23b5b928c305bf38144a4e33188bff80d/dblp}, booktitle = {HPCS}, crossref = {conf/ieeehpcs/2016}, ee = {http://dx.doi.org/10.1109/HPCSim.2016.7568360}, interhash = {e8beb37e2859536a4dae7c026bf5a6f7}, intrahash = {3b5b928c305bf38144a4e33188bff80d}, isbn = {978-1-5090-2088-1}, keywords = {dblp}, pages = {380-386}, publisher = {IEEE}, timestamp = {2016-10-05T11:37:14.000+0200}, title = {Modeling a switch architecture with virtual output queues and virtual channels in HPC-systems simulators.}, url = {http://dblp.uni-trier.de/db/conf/ieeehpcs/ieeehpcs2016.html#YebenesMEGQ16}, year = 2016 }