%0 Journal Article %1 journals/vlsi/BaileyM14 %A Bailey, Christopher %A Mullane, Brendan %D 2014 %J VLSI Design %K dblp %P 493189:1-493189:13 %T Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics. %U http://dblp.uni-trier.de/db/journals/vlsi/vlsi2014.html#BaileyM14 %V 2014

@article{journals/vlsi/BaileyM14, added-at = {2019-06-02T00:00:00.000+0200}, author = {Bailey, Christopher and Mullane, Brendan}, biburl = {https://www.bibsonomy.org/bibtex/26908354e6d7f95260396e9d2d7e7e721/dblp}, ee = {https://www.wikidata.org/entity/Q59101278}, interhash = {e9d1638374eb195ddcd8fcf3ee5c7a7b}, intrahash = {6908354e6d7f95260396e9d2d7e7e721}, journal = {VLSI Design}, keywords = {dblp}, pages = {493189:1-493189:13}, timestamp = {2019-06-04T11:47:18.000+0200}, title = {Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics.}, url = {http://dblp.uni-trier.de/db/journals/vlsi/vlsi2014.html#BaileyM14}, volume = 2014, year = 2014 }