Inproceedings,
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA.
Y. Ma, N. Suda, Y. Cao, J. sun Seo, and S. Vrudhula.FPL, page 1-8. IEEE, (2016)
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- conf/fpl/MaSCSV16
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- inproceedings
- booktitle
- FPL
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- 2016
- pages
- 1-8
- publisher
- IEEE
- crossref
- conf/fpl/2016
- ee
- https://doi.org/10.1109/FPL.2016.7577356
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- 978-2-8399-1844-2
- url
- http://dblp.uni-trier.de/db/conf/fpl/fpl2016.html#MaSCSV16
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- please select -%0 Conference Paper
%1 conf/fpl/MaSCSV16
%A Ma, Yufei
%A Suda, Naveen
%A Cao, Yu
%A sun Seo, Jae
%A Vrudhula, Sarma B. K.
%B FPL
%D 2016
%E Ienne, Paolo
%E Najjar, Walid A.
%E Anderson, Jason Helge
%E Brisk, Philip
%E Stechele, Walter
%I IEEE
%K dblp
%P 1-8
%T Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA.
%U http://dblp.uni-trier.de/db/conf/fpl/fpl2016.html#MaSCSV16
%@ 978-2-8399-1844-2
@inproceedings{conf/fpl/MaSCSV16,
added-at = {2022-08-16T00:00:00.000+0200},
author = {Ma, Yufei and Suda, Naveen and Cao, Yu and sun Seo, Jae and Vrudhula, Sarma B. K.},
biburl = {https://www.bibsonomy.org/bibtex/2820639129aebfef7a2616f36fb71e8de/dblp},
booktitle = {FPL},
crossref = {conf/fpl/2016},
editor = {Ienne, Paolo and Najjar, Walid A. and Anderson, Jason Helge and Brisk, Philip and Stechele, Walter},
ee = {https://doi.org/10.1109/FPL.2016.7577356},
interhash = {f05c314b474a3eb5427de78866791e05},
intrahash = {820639129aebfef7a2616f36fb71e8de},
isbn = {978-2-8399-1844-2},
keywords = {dblp},
pages = {1-8},
publisher = {IEEE},
timestamp = {2024-04-10T14:52:01.000+0200},
title = {Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA.},
url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2016.html#MaSCSV16},
year = 2016
}