%0 Conference Paper %1 conf/vlsic/RanicaPHWNCGNMI16 %A Ranica, Rossella %A Planes, Nicolas %A Huard, Vincent %A Weber, Olivier %A Noblet, Daniel %A Croain, Damien %A Giner, Fabien %A Naudet, Sylvie %A Mergault, P. %A Ibars, S. %A Villaret, A. %A Parra, Maryline %A Haendler, Sébastien %A Quoirin, M. %A Cacho, Florian %A Julien, C. %A Terrier, F. %A Ciampolini, Lorenzo %A Turgis, David %A Lecocq, Christophe %A Arnaud, Franck %B VLSI Circuits %D 2016 %I IEEE %K dblp %P 1-2 %T 28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#RanicaPHWNCGNMI16 %@ 978-1-5090-0635-9

@inproceedings{conf/vlsic/RanicaPHWNCGNMI16, added-at = {2022-09-29T00:00:00.000+0200}, author = {Ranica, Rossella and Planes, Nicolas and Huard, Vincent and Weber, Olivier and Noblet, Daniel and Croain, Damien and Giner, Fabien and Naudet, Sylvie and Mergault, P. and Ibars, S. and Villaret, A. and Parra, Maryline and Haendler, Sébastien and Quoirin, M. and Cacho, Florian and Julien, C. and Terrier, F. and Ciampolini, Lorenzo and Turgis, David and Lecocq, Christophe and Arnaud, Franck}, biburl = {https://www.bibsonomy.org/bibtex/2535d3d1b9a726ca2587d665a7446a6cf/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2016}, ee = {https://doi.org/10.1109/VLSIC.2016.7573512}, interhash = {faf4dae2afb74f8868dabf97dd35b49d}, intrahash = {535d3d1b9a726ca2587d665a7446a6cf}, isbn = {978-1-5090-0635-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-10T15:34:06.000+0200}, title = {28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#RanicaPHWNCGNMI16}, year = 2016 }