BibSonomy publications for /author/Vogel

]> BibSonomy publications for /author/Vogel http://www.bibsonomy.org/burst/author/Vogel BibSonomy BuRST Feed for /author/Vogel 2008-07-27T02:46:10+02:00 Comprehensive error analysis of combined channel mismatch effects in time-interleaved ADCs http://www.bibsonomy.org/bibtex/283d4c6978ddecfb11415c17d6d4415bd/peteru peteru 2008-07-15T17:04:25+02:00 adc, analysis, error, time-interleaved

Comprehensive error analysis of combined channel mismatch effects in time-interleaved ADCs

C. Vogel Instrumentation and Measurement Technology Conference, 2003. IMTC '03. Proceedings of the 20th IEEE 1 733--738 (2003)

to adc, analysis, error, time-interleaved by peteru on 2008-07-15 17:04:25 ]]> Instrumentation and Measurement Technology Conference, 2003. IMTC '03. Proceedings of the 20th IEEEInstrumentation and Measurement Technology Conference, 2003. IMTC '03. Proceedings of the 20th IEEE733--738Comprehensive error analysis of combined channel mismatch effects in time-interleaved ADCs12003adc, analysis, error, time-interleaved 2008-07-15 17:04:25.0 Analysis and compensation of nonlinearity mismatches in time-interleaved ADC arrays http://www.bibsonomy.org/bibtex/2b9b5525883dc4e76fdbbdfcab03f13c6/peteru peteru 2008-07-15T17:04:25+02:00 adc, interleaved, mismatches, nonlinearity, time

Analysis and compensation of nonlinearity mismatches in time-interleaved ADC arrays

C. Vogel and G. Kubin Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on 1 I--593-6 Vol.1 (2004)

to adc, interleaved, mismatches, nonlinearity, time by peteru on 2008-07-15 17:04:25 ]]> Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium onCircuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium onI--593-6 Vol.1Analysis and compensation of nonlinearity mismatches in time-interleaved ADC arrays12004adc, interleaved, mismatches, nonlinearity, time 2008-07-15 17:04:25.0Time-interleaved ADCs (TIADCs) are used to achieve high sampling rates. The drawback of such an architecture are mismatch effects, which decrease the signal-to-noise and distortion ratio (SINAD) and the spurious-free dynamic range (SFDR). Many papers have investigated the problem of mismatches but very few have considered he problem of nonlinearity mismatches. We present a mathematical framework for nonlinearity mismatches, describe their main characteristics, and show an effective compensation method to increase the SFDR. Compensation of timing mismatches in time-interleaved analog-to-digital converters through transfer characteristics tuning http://www.bibsonomy.org/bibtex/2ceb630956e853166152db391bbdcaa0f/peteru peteru 2008-07-15T17:04:25+02:00 adc, compensation, interleaved, mismatches, time, timing

Compensation of timing mismatches in time-interleaved analog-to-digital converters through transfer characteristics tuning

C. Vogel and D. Draxelmayr and F. Kuttner Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on 1 I--341-4 vol.1 (2004)

to adc, compensation, interleaved, mismatches, time, timing by peteru on 2008-07-15 17:04:25 ]]> Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium onCircuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium onI--341-4 vol.1Compensation of timing mismatches in time-interleaved analog-to-digital converters through transfer characteristics tuning12004adc, compensation, interleaved, mismatches, time, timing 2008-07-15 17:04:25.0We analyze transfer characteristic mismatches of sample-and-hold circuits in time-interleaved analog-to-digital converters and show their intrinsic connection to aperture delay mismatches. Both cause linear-phase mismatches, i.e., timing mismatches, which significantly degrade the signal-to-noise ratio. Based on our analysis, we introduce a novel power-saving method to correct timing mismatches among the channels by tuning the transfer characteristics of the sample-and-holds. Simulation results confirm the prospects of the presented method. A Novel Channel Randomization Method for Time-Interleaved ADCs http://www.bibsonomy.org/bibtex/2bb91dd00cf832e8d2d4632d8e58f69da/peteru peteru 2008-07-15T17:04:25+02:00 adc, channel, mismatch, optimization, randomization, shaping, spectral, time-interleaved

A Novel Channel Randomization Method for Time-Interleaved ADCs

C. Vogel and V. Pammer and G. Kubin Instrumentation and Measurement Technology Conference, 2005. IMTC 2005. Proceedings of the IEEE 1 150--155 (2005)

to adc, channel, mismatch, optimization, randomization, shaping, spectral, time-interleaved by peteru on 2008-07-15 17:04:25 ]]> Instrumentation and Measurement Technology Conference, 2005. IMTC 2005. Proceedings of the IEEEInstrumentation and Measurement Technology Conference, 2005. IMTC 2005. Proceedings of the IEEE150--155A Novel Channel Randomization Method for Time-Interleaved ADCs12005adc, channel, mismatch, optimization, randomization, shaping, spectral, time-interleaved 2008-07-15 17:04:25.0We introduce a novel randomization method for time-interleaved analog-to-digital converters (TIADCs). In contrast to conventional randomization methods our method improves the signal-to-noise and distortion ratio (SINAD) and the spurious free dynamic range (SFDR) by combining randomization of channel ADCs and spectral shaping of timing mismatches. The new method can exploit information about timing mismatches of the channel ADCs in order to optimize the randomized sequence. We provide the theoretical background, discuss aspects of the advanced randomization, and present simulation results Time-interleaved analog-to-digital converters: status and future directions http://www.bibsonomy.org/bibtex/269437a8a7364c53923c6f548f9b16b5f/peteru peteru 2008-07-15T17:04:25+02:00 ad, adc, analog-to-digital, analysis, compensation, converter, correction, error, gain, identification, methods, mismatches, modeling, offset, parallel, principles, status, time-interleaved

Time-interleaved analog-to-digital converters: status and future directions

C. Vogel and H. Johansson Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on 4 pp.+ (2006)

to ad, adc, analog-to-digital, analysis, compensation, converter, correction, error, gain, identification, methods, mismatches, modeling, offset, parallel, principles, status, time-interleaved by peteru on 2008-07-15 17:04:25 ]]> Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium onCircuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on4 pp.+Time-interleaved analog-to-digital converters: status and future directions2006ad, adc, analog-to-digital, analysis, compensation, converter, correction, error, gain, identification, methods, mismatches, modeling, offset, parallel, principles, status, time-interleaved 2008-07-15 17:04:25.0We discuss time-interleaved analog-to-digital converters (ADCs) as a prime example of merging analog and digital signal processing. A time-interleaved ADC (TI-ADC) consists of M parallel channel ADCs that alternately take samples from the input signal, where the sampling rate can be increased by the number of channels compared to a single channel. We recall the advantages of time interleaving and investigate the problems involved. In particular, we explain the error behavior of mismatches among the channels, which distort the output signal and reduce the system performance significantly, and provide a concise framework for dealing with them. Based on this analysis, we review the principle possibilities of calibrating TI-ADCs, where we point out the necessities and advantages of digital enhancement. To this end, we discuss open issues of channel mismatch identification as well as channel mismatch correction. A Compensation Method for Magnitude Response Mismatches in Two-channel Time-interleaved Analog-to-Digital Converters http://www.bibsonomy.org/bibtex/275579bf60fca1b185a8ca5cbad48e8b5/peteru peteru 2008-07-15T17:04:25+02:00 adc, compensation, converters, magnitude, mismatches, response, time-interleaved

A Compensation Method for Magnitude Response Mismatches in Two-channel Time-interleaved Analog-to-Digital Converters

S. Mendel and C. Vogel Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on 712--715 (2006)

to adc, compensation, converters, magnitude, mismatches, response, time-interleaved by peteru on 2008-07-15 17:04:25 ]]> Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference onElectronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on712--715A Compensation Method for Magnitude Response Mismatches in Two-channel Time-interleaved Analog-to-Digital Converters2006adc, compensation, converters, magnitude, mismatches, response, time-interleaved 2008-07-15 17:04:25.0Analog-to-digital converters (ADCs) are critical components of signal processing systems and one of the bottlenecks of modern telecommunication systems. Time-interleaved ADCs (TI-ADCs), in which multiple ADCs are combined, are an effective way to achieve high sampling rates in order to comply with modern telecommunication standards. The drawback of such TI-ADCs are additional errors that are due to mismatches among the channels, which degrade the overall performance. Several qualified methods have been proposed to compensate offset, static gain, and timing (or linear-phase) mismatches. However, an effective method to compensate frequency-dependent magnitude response mismatches is still missing. In this paper we consider the compensation of frequency-dependent magnitude response mismatches for a two-channel time-interleaved sampling system. A single linear-phase finite impulse response (FIR) filter cascaded by a single time-varying multiplier provides the magnitude response compensation so that the performance of a TI-ADC is no longer limited by linear channel mismatches. A Frequency Domain Method for Blind Identification of Timing Mismatches in Time-Interleaved ADCs http://www.bibsonomy.org/bibtex/26ad39f66382898a547e2b087b8ff5864/peteru peteru 2008-07-15T17:04:25+02:00 adc, identification, mismatches, offset, time, time-interleaved, timing

A Frequency Domain Method for Blind Identification of Timing Mismatches in Time-Interleaved ADCs

C. Vogel Norchip Conference, 2006. 24th 45--48 (2006)

to adc, identification, mismatches, offset, time, time-interleaved, timing by peteru on 2008-07-15 17:04:25 ]]> Norchip Conference, 2006. 24thNorchip Conference, 2006. 24th45--48A Frequency Domain Method for Blind Identification of Timing Mismatches in Time-Interleaved ADCs2006adc, identification, mismatches, offset, time, time-interleaved, timing 2008-07-15 17:04:25.0The performance of time-interleaved ADCs (TI-ADCs) mainly suffers from timing mismatches. We introduce an accurate blind timing mismatch identification for bandlimited, oversampled input signals, which is based on a frequency relation between the input signal and the sampled output signal and the fact that timing mismatches are generally small compared to the sampling period. We provide a detailed derivation of the method and discuss questions of implementation and complexity. Finally, we show the potential of the method through numerical simulations On the Compensation of Magnitude Response Mismatches in M-channel Time-interleaved ADCs http://www.bibsonomy.org/bibtex/25da908629735336e6f406f88bea054e8/peteru peteru 2008-07-15T17:04:25+02:00 ad, adc, compensation, converter, correction, magnitude, mismatches, repsonse, time-interleaved

On the Compensation of Magnitude Response Mismatches in M-channel Time-interleaved ADCs

S. Mendel and C. Vogel Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on 3375--3378 (2007)

to ad, adc, compensation, converter, correction, magnitude, mismatches, repsonse, time-interleaved by peteru on 2008-07-15 17:04:25 ]]> Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium onCircuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on3375--3378On the Compensation of Magnitude Response Mismatches in M-channel Time-interleaved ADCs2007ad, adc, compensation, converter, correction, magnitude, mismatches, repsonse, time-interleaved 2008-07-15 17:04:25.0Parallel time-interleaved analog-to-digital converters (TI-ADCs) are an attractive architecture to realize low-power and high-speed data conversion. As a drawback of such converters, mismatches between the channels impair their performance, e.g., the spurious free dynamic range (SFDR). One characteristic that varies among all channels is the magnitude response. The authors proposed a method to compensate magnitude response mismatches in two-channel TI-ADCs. In this paper the authors extend this method to an arbitrary number of channels, discuss a possible implementation, and evaluate its performance. For an M-channel TI-ADC the compensation method requires (M-1) linear-phase FIR filters with relatively short tap sizes and (M-1) multipliers to modulate the filter output. Simulations confirm the effectiveness of the proposed method. Time-Interleaved Digital-to-Analog Converters for UWB Signal Generation http://www.bibsonomy.org/bibtex/2ceae58bba257cae1d78a4cf56ee65874/peteru peteru 2008-07-15T17:04:25+02:00 converter, dac, digital-to-analog, generator, signal, time-interleaved, uwb

Time-Interleaved Digital-to-Analog Converters for UWB Signal Generation

C. Krall and C. Vogel and K. Witrisal Ultra-Wideband, 2007. ICUWB 2007. IEEE International Conference on 366--371 (2007)

to converter, dac, digital-to-analog, generator, signal, time-interleaved, uwb by peteru on 2008-07-15 17:04:25 ]]> Ultra-Wideband, 2007. ICUWB 2007. IEEE International Conference onUltra-Wideband, 2007. ICUWB 2007. IEEE International Conference on366--371Time-Interleaved Digital-to-Analog Converters for UWB Signal Generation2007converter, dac, digital-to-analog, generator, signal, time-interleaved, uwb 2008-07-15 17:04:25.0In this paper, a differentially encoded time-interleaved digital-to-analog converter (TIDAC) structure for ultra-wideband (UWB) signal generation is presented. We show that the output spectrum of the TIDAC is identical to the output of a DAC running at a higher sampling rate. To support the mathematical derivations, the UWB signal generator has been implemented on FPGA hardware and measurements have been taken for a sinusoidal wave, a Gaussian UWB pulse shape and for a UWB OFDM signal. The measurements show that, compared to the single-channel DAC, the mirror images around the sampling frequency can be reduced by about 30 dB and the analog interpolation filter design is simplified. A z-domain model and analysis of phase-domain all-digital phase-locked loops http://www.bibsonomy.org/bibtex/2acd16bc6f8a7e217af72733a19c28c0b/peteru peteru 2008-07-15T17:04:25+02:00 adpll, all-digital, analysis, loops, model, phase-locked, pll, z-domain

A z-domain model and analysis of phase-domain all-digital phase-locked loops

S. Mendel and C. Vogel Norchip, 2007 1--6 (2007)

to adpll, all-digital, analysis, loops, model, phase-locked, pll, z-domain by peteru on 2008-07-15 17:04:25 ]]> Norchip, 2007Norchip, 20071--6A z-domain model and analysis of phase-domain all-digital phase-locked loops2007adpll, all-digital, analysis, loops, model, phase-locked, pll, z-domain 2008-07-15 17:04:25.0In this paper a comprehensive z-domain model of all-digital phase-locked loops (ADPLLs) is derived. The model accounts for phase and frequency signals and thus reflects both, frequency and phase behavior. The system model is investigated in detail. Each component is described in form of its transfer function to obtain an overall input/output behavior for the frequency and the phase domain. Furthermore, the physical characteristics of the noise sources within the structure are studied and their effects on the phase noise of the PLL are determined. The system level model is independent of the actual implementation, however, the relation to an existing frequency synthesizer for wireless communications is discussed. Simulation results confirm the accurateness of the presented model with respect to the time and frequency behavior of the system.