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AuthorTitleYearJournal/ProceedingsReftypeDOI/URL
Albu, F., Kadlec, J., Softley, C. I., Matousek, R., Hermanek, A., Coleman, N. & Fagan, A. Implementation of (Normalised) RLS Lattice on Virtex.

[BibTeX]

 2001 FPL   inproceedings URL  
BibTeX: 
@inproceedings{conf/fpl/AlbuKSMHCF01,
  author = {Felix Albu and Jiri Kadlec and Christopher I. Softley and Rudolf Matousek and Antonin Hermanek and Nick Coleman and Anthony Fagan},
  title = {Implementation of (Normalised) RLS Lattice on Virtex.},
  booktitle = {FPL},
  publisher = {Springer},
  year = {2001},
  volume = {2147},
  pages = {91-100},
  url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2001.html#AlbuKSMHCF01}
}
Athanas, P. M. The (empty?) Promise of FPGA Supercomputing.

[BibTeX]

 2006 Dynamically Reconfigurable Architectures   inproceedings URL  
BibTeX: 
@inproceedings{conf/dagstuhl/Athanas06,
  author = {Peter M. Athanas},
  title = {The (empty?) Promise of FPGA Supercomputing.},
  booktitle = {Dynamically Reconfigurable Architectures},
  publisher = {Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany},
  year = {2006},
  volume = {06141},
  url = {http://dblp.uni-trier.de/db/conf/dagstuhl/P6141.html#Athanas06}
}
Becker, J., Hübner, M. & Paulsson, K. Physical 2D Morphware and Power Reduction Methods for Everyone.

[BibTeX]

 2006 Dynamically Reconfigurable Architectures   inproceedings URL  
BibTeX: 
@inproceedings{conf/dagstuhl/BeckerHP06,
  author = {Jürgen Becker and Michael Hübner and Katarina Paulsson},
  title = {Physical 2D Morphware and Power Reduction Methods for Everyone.},
  booktitle = {Dynamically Reconfigurable Architectures},
  publisher = {Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany},
  year = {2006},
  volume = {06141},
  url = {http://dblp.uni-trier.de/db/conf/dagstuhl/P6141.html#BeckerHP06}
}
Becker, J., Teich, J., Brebner, G. J. & Athanas, P. M. 06141 Executive Summary -- Dynamically Reconfigurable Architectures.

[BibTeX]

 2006 Dynamically Reconfigurable Architectures   inproceedings URL  
BibTeX: 
@inproceedings{conf/dagstuhl/BeckerTBA06,
  author = {Jürgen Becker and Jürgen Teich and Gordon J. Brebner and Peter M. Athanas},
  title = {06141 Executive Summary -- Dynamically Reconfigurable Architectures.},
  booktitle = {Dynamically Reconfigurable Architectures},
  publisher = {Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany},
  year = {2006},
  volume = {06141},
  url = {http://dblp.uni-trier.de/db/conf/dagstuhl/P6141.html#BeckerTBA06}
}
Brebner, G. J. Configurable array logic circuits for computing network error detection codes.

[BibTeX]

 1993 VLSI Signal Processing   article URL  
BibTeX: 
@article{journals/vlsisp/Brebner93,
  author = {Gordon J. Brebner},
  title = {Configurable array logic circuits for computing network error detection codes.},
  journal = {VLSI Signal Processing},
  year = {1993},
  volume = {6},
  number = {2},
  pages = {101-117},
  url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp6.html#Brebner93}
}
Brebner, P. Performance modeling for service oriented architectures.

[BibTeX]

 2008 ICSE Companion   inproceedings URL  
BibTeX: 
@inproceedings{conf/icse/Brebner08,
  author = {Paul Brebner},
  title = {Performance modeling for service oriented architectures.},
  booktitle = {ICSE Companion},
  publisher = {ACM},
  year = {2008},
  pages = {953-954},
  url = {http://dblp.uni-trier.de/db/conf/icse/icsec2008.html#Brebner08}
}
Fischaber, S., Hasson, R., McAllister, J. & Woods, R. FPGA Core Network Implementation and Optimization: A Case Study.

[BibTeX]

 2005 FPT   inproceedings URL  
BibTeX: 
@inproceedings{conf/fpt/FischaberHMW05,
  author = {Scott Fischaber and R. Hasson and John McAllister and Roger Woods},
  title = {FPGA Core Network Implementation and Optimization: A Case Study.},
  booktitle = {FPT},
  publisher = {IEEE},
  year = {2005},
  pages = {319-320},
  url = {http://dblp.uni-trier.de/db/conf/fpt/fpt2005.html#FischaberHMW05}
}
Stechele, W. Dynamically Reconfigurable Systems-on-Chip.

[BibTeX]

 2006 Dynamically Reconfigurable Architectures   inproceedings URL  
BibTeX: 
@inproceedings{conf/dagstuhl/Stechele06,
  author = {Walter Stechele},
  title = {Dynamically Reconfigurable Systems-on-Chip.},
  booktitle = {Dynamically Reconfigurable Architectures},
  publisher = {Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany},
  year = {2006},
  volume = {06141},
  url = {http://dblp.uni-trier.de/db/conf/dagstuhl/P6141.html#Stechele06}
}
Vásárhelyi, J. & Serfözö, P. Analysis of Mojette Transform Implementation on Reconfigurable Hardware.

[BibTeX]

 2006 Dynamically Reconfigurable Architectures   inproceedings URL  
BibTeX: 
@inproceedings{conf/dagstuhl/VasarhelyiS06,
  author = {József Vásárhelyi and Péter Serfözö},
  title = {Analysis of Mojette Transform Implementation on Reconfigurable Hardware.},
  booktitle = {Dynamically Reconfigurable Architectures},
  publisher = {Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany},
  year = {2006},
  volume = {06141},
  url = {http://dblp.uni-trier.de/db/conf/dagstuhl/P6141.html#VasarhelyiS06}
}
Wehn, N., Vogt, T. & Neeb, C. A Reconfigurable Outer Modem Platform for Future Communications Systems.

[BibTeX]

 2006 Dynamically Reconfigurable Architectures   inproceedings URL  
BibTeX: 
@inproceedings{conf/dagstuhl/WehnVN06,
  author = {Norbert Wehn and Timo Vogt and Christian Neeb},
  title = {A Reconfigurable Outer Modem Platform for Future Communications Systems.},
  booktitle = {Dynamically Reconfigurable Architectures},
  publisher = {Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany},
  year = {2006},
  volume = {06141},
  url = {http://dblp.uni-trier.de/db/conf/dagstuhl/P6141.html#WehnVN06}
}

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