| Author | Title | Year | Journal/Proceedings | Reftype | DOI/URL |
|---|---|---|---|---|---|
| Bjerregaard, T. & Sparsø, J. | Packetizing OCP Transactions in the MANGO Network-on-Chip. [BibTeX] |
2006 | DSD, pp. 657-664 | inproceedings | URL |
BibTeX:
@inproceedings{conf/dsd/BjerregaardS06,
author = {Tobias Bjerregaard and Jens Sparsø},
title = {Packetizing OCP Transactions in the MANGO Network-on-Chip.},
booktitle = {DSD},
publisher = {IEEE Computer Society},
year = {2006},
pages = {657-664},
url = {http://dblp.uni-trier.de/db/conf/dsd/dsd2006.html#BjerregaardS06}
}
|
|||||
| Bjerregaard, T., Stensgaard, M.B. & Sparsø, J. | A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method. [BibTeX] |
2007 | DATE, pp. 648-653 | inproceedings | URL |
BibTeX:
@inproceedings{conf/date/BjerregaardSS07,
author = {Tobias Bjerregaard and Mikkel Bystrup Stensgaard and Jens Sparsø},
title = {A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method.},
booktitle = {DATE},
publisher = {ACM},
year = {2007},
pages = {648-653},
url = {http://dblp.uni-trier.de/db/conf/date/date2007.html#BjerregaardSS07}
}
|
|||||
| Mahadevan, S., Angiolini, F., Sparsø, J., Benini, L. & Madsen, J. | A Reactive and Cycle-True IP Emulator for MPSoC Exploration. [BibTeX] |
2008 | IEEE Trans. on CAD of Integrated Circuits and Systems Vol. 27(1), pp. 109-122 |
article | URL |
BibTeX:
@article{journals/tcad/MahadevanASBM08,
author = {Shankar Mahadevan and Federico Angiolini and Jens Sparsø and Luca Benini and Jan Madsen},
title = {A Reactive and Cycle-True IP Emulator for MPSoC Exploration.},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
year = {2008},
volume = {27},
number = {1},
pages = {109-122},
url = {http://dblp.uni-trier.de/db/journals/tcad/tcad27.html#MahadevanASBM08}
}
|
|||||
| Mahadevan, S., Angiolini, F., Sparsø, J., Benini, L. & Madsen, J. | A Traffic Injection Methodology with Support for System-Level Synchronization. [BibTeX] |
2005 | Vol. 240VLSI-SoC, pp. 145-161 |
inproceedings | URL |
BibTeX:
@inproceedings{conf/vlsi/MahadevanASBM05,
author = {Shankar Mahadevan and Federico Angiolini and Jens Sparsø and Luca Benini and Jan Madsen},
title = {A Traffic Injection Methodology with Support for System-Level Synchronization.},
booktitle = {VLSI-SoC},
publisher = {Springer},
year = {2005},
volume = {240},
pages = {145-161},
url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2005.html#MahadevanASBM05}
}
|
|||||
| Nielsen, L.S., Niessen, C., Sparsø, J. & van Berkel, K. | Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. [BibTeX] |
1994 | IEEE Trans. VLSI Syst. Vol. 2(4), pp. 391-397 |
article | URL |
BibTeX:
@article{journals/tvlsi/NielsenNSB94,
author = {Lars Skovby Nielsen and C. Niessen and Jens Sparsø and K. van Berkel},
title = {Low-power operation using self-timed circuits and adaptive scaling of the supply voltage.},
journal = {IEEE Trans. VLSI Syst.},
year = {1994},
volume = {2},
number = {4},
pages = {391-397},
url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi2.html#NielsenNSB94}
}
|
|||||
| Oklobdzija, V.G. & Sparsø, J. | Future directions in clocking multi-ghz systems. [BibTeX] |
2002 | ISLPED, pp. 219 | inproceedings | URL |
BibTeX:
@inproceedings{conf/islped/OklobdzijaS02,
author = {Vojin G. Oklobdzija and Jens Sparsø},
title = {Future directions in clocking multi-ghz systems.},
booktitle = {ISLPED},
publisher = {ACM},
year = {2002},
pages = {219},
url = {http://dblp.uni-trier.de/db/conf/islped/islped2002.html#OklobdzijaS02}
}
|
|||||
| Paker, Ö., Sparsø, J., Haandbæk, N., Isager, M. & Nielsen, L.S. | A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing. [BibTeX] |
2004 | VLSI Signal Processing Vol. 37(1), pp. 95-110 |
article | URL |
BibTeX:
@article{journals/vlsisp/PakerSHIN04,
author = {Özgün Paker and Jens Sparsø and Niels Haandbæk and Mogens Isager and Lars Skovby Nielsen},
title = {A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing.},
journal = {VLSI Signal Processing},
year = {2004},
volume = {37},
number = {1},
pages = {95-110},
url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp37.html#PakerSHIN04}
}
|
|||||
| Sparsø, J., Nielsen, C.D., Nielsen, L.S. & Staunstrup, J. | Design of Self-timed Multipliers: A Comparison. [BibTeX] |
1993 | Vol. A-28Asynchronous Design Methodologies, pp. 165-179 |
inproceedings | URL |
BibTeX:
@inproceedings{conf/ifip10-5/SparsoNNS93,
author = {Jens Sparsø and Christian D. Nielsen and Lars Skovby Nielsen and Jørgen Staunstrup},
title = {Design of Self-timed Multipliers: A Comparison.},
booktitle = {Asynchronous Design Methodologies},
publisher = {North-Holland},
year = {1993},
volume = {A-28},
pages = {165-179},
url = {http://dblp.uni-trier.de/db/conf/ifip10-5/ifip10-5-1993.html#SparsoNNS93}
}
|
|||||
| Stensgaard, M.B., Bjerregaard, T., Sparsø, J. & Pedersen, J.H. | A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip. [BibTeX] |
2006 | DSD, pp. 641-648 | inproceedings | URL |
BibTeX:
@inproceedings{conf/dsd/StensgaardBSP06,
author = {Mikkel Bystrup Stensgaard and Tobias Bjerregaard and Jens Sparsø and Johnny Halkjær Pedersen},
title = {A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip.},
booktitle = {DSD},
publisher = {IEEE Computer Society},
year = {2006},
pages = {641-648},
url = {http://dblp.uni-trier.de/db/conf/dsd/dsd2006.html#StensgaardBSP06}
}
|
|||||
| Stensgaard, M.B. & Sparsø, J. | ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology. [BibTeX] |
2008 | NOCS, pp. 55-64 | inproceedings | URL |
BibTeX:
@inproceedings{conf/nocs/StensgaardS08,
author = {Mikkel Bystrup Stensgaard and Jens Sparsø},
title = {ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology.},
booktitle = {NOCS},
publisher = {IEEE Computer Society},
year = {2008},
pages = {55-64},
url = {http://dblp.uni-trier.de/db/conf/nocs/nocs2008.html#StensgaardS08}
}
|
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Created by JabRef on 01/12/2008.