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A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology.

P. Upadhyaya, A. Bekele, D. Melek, H. Zhao, J. Im, J. Cho, K. Tan, S. McLeod, S. Chen, W. Zhang, Y. Frans, and K. Chang. VLSI Circuits, page 1-2. IEEE, (2016)

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Yohan Shim

Yohan Seo

Yohan Lejosne

Fekadu Yohannes

Indra Yohannes

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ADC-based Wireline Transceiver.Y. Frans. CICC, page 1-89. IEEE, (2019)A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET.M. Erett, J. Hudner, D. Carey, R. Casey, K. Geary, K. Hearne, P. Neto, T. Mallard, V. Sooden, M. Smyth and 7 other author(s). IEEE J. Solid State Circuits, 52 (7): 1783-1797 (2017)Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET.M. Raj, Y. Frans, P. Chiang, S. Ambatipudi, D. Mahashin, P. Heyn, S. Balakrishnan, J. Campenhout, J. Grayson, M. Epitaux and 1 other author(s). IEEE J. Solid State Circuits, 55 (4): 1086-1095 (2020)Session 8 Overview: Ultra-High-Speed Wireline Wireline Subcommittee.Y. Frans, P. Yue, and T. Toifl. ISSCC, page 124-125. IEEE, (2021)3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS.P. Upadhyaya, J. Savoj, F. An, A. Bekele, A. Jose, B. Xu, Z. Wu, D. Turker, H. Aslanzadeh, H. Hedayati and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.P. Upadhyaya, C. Poon, S. Lim, J. Cho, A. Roldan, W. Zhang, J. Namkoong, T. Pham, B. Xu, W. Lin and 6 other author(s). IEEE J. Solid State Circuits, 54 (1): 18-28 (2019)A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.H. Lee, K. Chang, J. Chun, T. Wu, Y. Frans, B. Leibowitz, N. Nguyen, T. Chin, K. Kaviani, J. Shen and 10 other author(s). IEEE J. Solid State Circuits, 44 (4): 1235-1247 (2009)A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET.M. Raj, Y. Frans, S. Ambatipudi, D. Mahashin, P. Heyn, S. Balakrishnan, J. Campenhout, J. Grayson, M. Epitaux, and K. Chang. VLSI Circuits, page 190-. IEEE, (2019)A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET.J. Im, D. Freitas, A. Roldan, R. Casey, S. Chen, A. Chou, T. Cronin, K. Geary, S. McLeod, L. Zhou and 7 other author(s). IEEE J. Solid State Circuits, 52 (12): 3486-3502 (2017)A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling.B. Leibowitz, R. Palmer, J. Poulton, Y. Frans, S. Li, J. Wilson, M. Bucher, A. Fuller, J. Eyles, M. Aleksic and 2 other author(s). IEEE J. Solid State Circuits, 45 (4): 889-898 (2010)

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Disambiguation of "Frans, Yohan"

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A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology.

Please choose a person to relate this publication to

Yohan Shim

Yohan Seo

Yohan Lejosne

Fekadu Yohannes

Indra Yohannes

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Frans, Yohan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology.

Please choose a person to relate this publication to

Yohan Shim

Yohan Seo

Yohan Lejosne

Fekadu Yohannes

Indra Yohannes

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology.