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Disambiguation of "Ozaki, Hideyuki"

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Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode.

, , , , , and . ITC, page 826-829. IEEE Computer Society, (1986)

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Hideyuki Sakamoto

 

Other publications of authors with the same name

A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories., , , , , , , , and . IEEE J. Solid State Circuits, 31 (4): 575-585 (1996)An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs., , , , , , and . IEEE J. Solid State Circuits, 29 (4): 534-538 (April 1994)An adjustable output driver with a self-recovering Vpp generator for a 4M⨉16 DRAM., , , , and . IEEE J. Solid State Circuits, 29 (3): 308-310 (March 1994)A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory., , and . IEEE J. Solid State Circuits, 31 (4): 523-530 (1996)A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros., , , , , , , , , and 2 other author(s). IEICE Trans. Electron., 88-C (10): 2020-2027 (2005)A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs., , , , , and . IEEE J. Solid State Circuits, 35 (8): 1179-1185 (2000)High-performance embedded SOI DRAM architecture for the low-power supply., , , , , , and . IEEE J. Solid State Circuits, 35 (8): 1169-1178 (2000)400-MHz random column operating SDRAM techniques with self-skew compensation., , , , , , and . IEEE J. Solid State Circuits, 33 (5): 770-778 (1998)Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode., , , , , and . ITC, page 826-829. IEEE Computer Society, (1986)A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 35 (11): 1680-1689 (2000)