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s read throughput.

K. Yasufuku, N. Oshiyama, T. Saito, Y. Miyamoto, Y. Nakamura, R. Terauchi, A. Kondo, T. Aoyama, M. Takahashi, Y. Oowaki, and R. Bandai. A-SSCC, page 29-32. IEEE, (2014)

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Yukihito Kuroyanagi

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Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI.Y. Oowaki, S. Shiratake, T. Fujiyoshi, M. Hamada, F. Hatori, M. Murakata, and M. Takahashi. IEICE Trans. Electron., 89-C (3): 263-270 (2006)A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling.T. Fujiyoshi, S. Shiratake, S. Nomura, T. Nishikawa, Y. Kitasho, H. Arakida, Y. Okuda, Y. Tsuboi, M. Hamada, H. Hara and 13 other author(s). IEEE J. Solid State Circuits, 41 (1): 54-62 (2006)Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems.C. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, and Y. Oowaki. IEEE Trans. Very Large Scale Integr. Syst., 14 (12): 1379-1383 (2006)An automated runtime power-gating scheme.M. Hamada, T. Kitahara, N. Kawabe, H. Sato, T. Nishikawa, T. Shimazawa, T. Yamashita, H. Hara, and Y. Oowaki. ICCD, page 382-387. IEEE, (2007)A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM.Y. Kikuchi, M. Takahashi, T. Maeda, M. Fukuda, Y. Koshio, H. Hara, H. Arakida, H. Yamamoto, Y. Hagiwara, T. Fujita and 8 other author(s). IEEE J. Solid State Circuits, 46 (1): 32-41 (2011)Development of low power and high performance application processor (T6G) for multimedia mobile applications.Y. Kitasho, Y. Kikuchi, T. Shimazawa, Y. Ohara, M. Takahashi, Y. Masubuchi, and Y. Oowaki. ASP-DAC, page 755-759. IEEE, (2011)A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput.K. Yasufuku, N. Oshiyama, T. Saito, Y. Miyamoto, Y. Nakamura, R. Terauchi, A. Kondo, T. Aoyama, M. Takahashi, Y. Oowaki and 1 other author(s). A-SSCC, page 29-32. IEEE, (2014)19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension.K. Watanabe, K. Yoshii, N. Kondo, K. ichi Maeda, T. Fujisawa, J. Wadatsumi, D. Miyashita, S. Kousai, Y. Unekawa, S. Fujii and 4 other author(s). ISSCC, page 330-331. IEEE, (2014)Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's.D. Takashima, Y. Oowaki, S. Watanabe, and K. Ohuchi. IEEE J. Solid State Circuits, 33 (2): 260-267 (1998)Open/folded bit-line arrangement for ultra-high-density DRAM's.D. Takashima, S. Watanabe, H. Nakano, Y. Oowaki, and K. Ohuchi. IEEE J. Solid State Circuits, 29 (4): 539-542 (April 1994)

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Disambiguation of "Oowaki, Yukihito"

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A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput.

Please choose a person to relate this publication to

Yukihito Kuroyanagi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Oowaki, Yukihito"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput.

Please choose a person to relate this publication to

Yukihito Kuroyanagi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput.