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A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.

E. Beigné, A. Valentian, I. Panades, R. Wilson, P. Flatresse, F. Abouzeid, T. Benoist, C. Bernard, S. Bernard, O. Billoint, S. Clerc, B. Giraud, A. Grover, J. Coz, J. Noel, O. Thomas, and Y. Thonnart. IEEE J. Solid State Circuits, 50 (1): 125-136 (2015)

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Alexandre Varnek

Alexandre Martins

Alexandre Darmoise

Alexandre Alexeev

Alexandre Jousset

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Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits.S. Houri, G. Billiot, M. Belleville, A. Valentian, and H. Fanet. RC, volume 9138 of Lecture Notes in Computer Science, page 267-272. Springer, (2015)An Asynchronous Power Aware and Adaptive NoC Based Circuit.E. Beigné, F. Clermidy, H. Lhermet, S. Miermont, Y. Thonnart, X. Tran, A. Valentian, D. Varreau, P. Vivet, X. Popon and 1 other author(s). IEEE J. Solid State Circuits, 44 (4): 1167-1177 (2009)Design challenges for nano-scale devices.M. Belleville, O. Thomas, A. Valentian, and F. Clermidy. ESSDERC, page 69-72. IEEE, (2012)Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology.B. Pelloux-Prayer, A. Valentian, B. Giraud, Y. Thonnart, J. Noel, P. Flatresse, and E. Beigné. VLSI-SoC, page 168-173. IEEE, (2013)Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec.J. Coz, P. Flatresse, S. Engels, A. Valentian, M. Belleville, C. Raynaud, D. Croain, and P. Urard. ISSCC, page 336-337. IEEE, (2011)2021 Roadmap on Neuromorphic Computing and Engineering.D. Christensen, R. Dittmann, B. Linares-Barranco, A. Sebastian, M. Gallo, A. Redaelli, S. Slesazeck, T. Mikolajick, S. Spiga, S. Menzel and 46 other author(s). CoRR, (2021)Investigating Current-Based and Gating Approaches for Accurate and Energy-Efficient Spiking Recurrent Neural Networks.M. Dampfhoffer, T. Mesquida, A. Valentian, and L. Anghel. ICANN (3), volume 13531 of Lecture Notes in Computer Science, page 359-370. Springer, (2022)A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs.E. Beigné, F. Clermidy, S. Miermont, A. Valentian, P. Vivet, S. Barasinski, F. Blisson, N. Kohli, and S. Kumar. ESSCIRC, page 138-141. IEEE, (2008)UTBB FDSOI technology flexibility for ultra low power internet-of-things applications.E. Beigné, J. Christmann, A. Valentian, O. Billoint, E. Amat, and D. Morche. ESSDERC, page 164-167. IEEE, (2015)A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations.S. Bernard, A. Valentian, D. Bol, J. Legat, and M. Belleville. J. Low Power Electron., 10 (1): 118-126 (2014)

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Disambiguation of "Valentian, Alexandre"

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A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.

Please choose a person to relate this publication to

Alexandre Varnek

Alexandre Martins

Alexandre Darmoise

Alexandre Alexeev

Alexandre Jousset

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Valentian, Alexandre"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.

Please choose a person to relate this publication to

Alexandre Varnek

Alexandre Martins

Alexandre Darmoise

Alexandre Alexeev

Alexandre Jousset

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.