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Disambiguation of "Panda, Preeti Ranjan"

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Augmenting Loop Tiling with Data Alignment for Improved Cache Performance.

, , , and . IEEE Trans. Computers, 48 (2): 142-149 (1999)

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Preeti Bajaj

Satyananda Panda

Preeti Kumari

Preeti Sareen

Preeti Bhargava

 

Other publications of authors with the same name

Compressing Cache State for Postsilicon Processor Debug., , and . IEEE Trans. Computers, 60 (4): 484-497 (2011)Reusing trace buffers to enhance cache performance., , and . DATE, page 572-577. IEEE, (2017)Cache aware compression for processor debug support., , and . DATE, page 208-213. IEEE, (2009)Abridged addressing: a low power memory addressing strategy.. ASP-DAC, page 892-897. IEEE, (2006)Managing Trace Summaries to Minimize Stalls During Postsilicon Validation., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (6): 1881-1894 (2017)Guest Editor Introduction: Special Issue on Multiprocessor-based Embedded Systems.. Int. J. Parallel Program., 36 (1): 1-2 (2008)An integrated algorithm for memory allocation and assignment in high-level synthesis., , and . DAC, page 608-611. ACM, (2002)Array Interleaving - An Energy-Efficient Data Layout Transformation., , , , and . ACM Trans. Design Autom. Electr. Syst., 20 (3): 44:1-44:26 (2015)FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation., , , and . CODES+ISSS, page 247-256. ACM, (2010)A Special Issue on the "22nd IEEE International Conference on VLSI Design" New Delhi, India, 5-9 January 2009., and . J. Low Power Electron., 5 (3): 255-256 (2009)