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Achieving One Billion Key-Value Requests per Second on a Single Server.

S. Li, H. Lim, V. Lee, J. Ahn, A. Kalia, M. Kaminsky, D. Andersen, S. O, S. Lee, and P. Dubey. IEEE Micro, 36 (3): 94-104 (2016)

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O Manuwald

O Nommensen

O Otsuka

O Hampe

O Deutschmann

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Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product.S. Lee, S. Kang, J. Lee, H. Kim, E. Lee, S. Seo, H. Yoon, S. Lee, K. Lim, H. Shin and 6 other author(s). ISCA, page 43-56. IEEE, (2021)History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures.K. Chen, S. Li, J. Ahn, N. Muralimanohar, J. Zhao, C. Xu, S. O, Y. Xie, J. Brockman, and N. Jouppi. ICS, page 251-261. ACM, (2015)A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process.D. Kim, B. Song, H. Ahn, W. Ko, S. Do, S. Cho, K. Kim, S. Oh, H. Joo, G. Park and 37 other author(s). ISSCC, page 448-450. IEEE, (2022)Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems.Y. Son, S. O, H. Yang, D. Jung, J. Ahn, J. Kim, J. Kim, and J. Lee. SC, page 1059-1070. IEEE Computer Society, (2014)Reducing memory access latency with asymmetric DRAM bank organizations.Y. Son, S. O, Y. Ro, J. Lee, and J. Ahn. ISCA, page 380-391. ACM, (2013)3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions.S. Lee, K. Lee, M. Sung, M. Alian, C. Kim, W. Cho, R. Oh, S. O, J. Ahn, and N. Kim. PACT, page 22:1-22:12. ACM, (2018)CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults.S. O, S. Kwon, Y. Son, Y. Park, and J. Ahn. IEEE Comput. Archit. Lett., 14 (1): 17-20 (2015)Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices.S. uhn Cha, S. O, H. Shin, S. Hwang, K. Park, S. Jang, J. Choi, G. Jin, Y. Son, H. Cho and 2 other author(s). HPCA, page 61-72. IEEE Computer Society, (2017)Row-buffer decoupling: A case for low-latency DRAM microarchitecture.S. O, Y. Son, N. Kim, and J. Ahn. ISCA, page 337-348. IEEE Computer Society, (2014)McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling.J. Ahn, S. Li, S. O, and N. Jouppi. ISPASS, page 74-85. IEEE Computer Society, (2013)

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Disambiguation of "O, Seongil"

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Achieving One Billion Key-Value Requests per Second on a Single Server.

Please choose a person to relate this publication to

O Manuwald

O Nommensen

O Otsuka

O Hampe

O Deutschmann

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "O, Seongil"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Achieving One Billion Key-Value Requests per Second on a Single Server.

Please choose a person to relate this publication to

O Manuwald

O Nommensen

O Otsuka

O Hampe

O Deutschmann

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
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URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Achieving One Billion Key-Value Requests per Second on a Single Server.