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Disambiguation of "Flores, Paulo F."

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Multicore SIMD ASIP for Next-Generation Sequencing and Alignment Biochip Platforms.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (7): 1287-1300 (2015)

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Milan Paulovic

Manuel António Paulo

Hartwig Paulo

Kurt Paulokat

Nicola Paulo

 

Other publications of authors with the same name

Optimized ASIP architecture for compressed BWT-indexed search in bioinformatics applications., , and . HPCS, page 527-534. IEEE, (2014)Compact CMOS-Compatible Majority Gate Using Body Biasing in FDSOI Technology., , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 13 (1): 86-95 (March 2023)Multiplierless Design of Folded DSP Blocks., , and . ACM Trans. Design Autom. Electr. Syst., 20 (1): 14:1-14:24 (2014)Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming., , , and . DAC, page 669-674. ACM, (2006)Optimization of gate-level area in high throughput Multiple Constant Multiplications., , , and . ECCTD, page 588-591. IEEE, (2011)Exploration of tradeoffs in the design of integer cosine transforms for image compression., , , and . ECCTD, page 1-4. IEEE, (2013)ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis., , , and . ICECS, page 748-751. IEEE, (2006)Efficient shift-adds design of digit-serial multiple constant multiplications., , , , and . ACM Great Lakes Symposium on VLSI, page 61-66. ACM, (2011)An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications., , and . ICCAD, page 13-16. IEEE Computer Society, (2005)A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures., , and . Circuits Syst. Signal Process., 33 (6): 1689-1719 (2014)