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Performance Scaling of Cassandra on High-Thread Count Servers., , , and . ICPE, page 179-187. ACM, (2019)Design of high-performance system-on-chips using communication architecture tuners., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (5): 620-636 (2004)Communication-Based Power Management., , and . IEEE Des. Test Comput., 19 (4): 118-130 (2002)Battery discharge characteristics of wireless sensor nodes: an experimental analysis., , and . SECON, page 430-440. IEEE, (2005)Performance Analysis of Systems with Multi-Channel Communication Architectures., , and . VLSI Design, page 530-537. IEEE Computer Society, (2000)Power analysis of system-level on-chip communication architectures., and . CODES+ISSS, page 236-241. ACM, (2004)Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation., , and . DAC, page 883-886. IEEE, (2007)System-level performance analysis for designing on-chipcommunication architectures., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (6): 768-783 (2001)Efficient power profiling for battery-driven embedded system design., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (6): 919-932 (2004)Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design., , , and . ASP-DAC/VLSI Design, page 261-267. IEEE Computer Society, (2002)