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Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients., , , , , , and . DAC, page 399-404. ACM, (2002)Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits., , , , , , and . IEEE J. Solid State Circuits, 37 (11): 1383-1395 (2002)Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 40 (9): 1922-1931 (2005)Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate., , , , , , , , and . IEEE J. Solid State Circuits, 39 (7): 1119-1130 (2004)High-Level Power Minimization of Analog Sensor Interface Architectures., , and . Integr. Comput. Aided Eng., 5 (4): 303-314 (1998)Digital ground bounce reduction by supply current shaping and clock frequency Modulation., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (1): 65-76 (2005)Compensation of transmitter IQ imbalance for OFDM systems., , , , , and . ICASSP (2), page 325-328. IEEE, (2004)OFDM versus Single Carrier with Cyclic Prefix: a system-based comparison., , , , , and . VTC Fall, page 1115-1119. IEEE, (2001)Digital Ground Bounce Reduction by Phase Modulation of the Clock., , , , , and . DATE, page 88-93. IEEE Computer Society, (2004)A Single-Package Solution for Wireless Transceivers., , , , , and . DATE, page 425-. IEEE Computer Society / ACM, (1999)