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RLC effects on worst-case switching pattern for on-chip buses.

, , and . ISCAS (2), page 945-948. IEEE, (2004)

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Layout techniques for on-chip interconnect inductance reduction., , and . ASP-DAC, page 269-273. IEEE Computer Society, (2004)RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (10): 2258-2264 (2006)RLC effects on worst-case switching pattern for on-chip buses., , and . ISCAS (2), page 945-948. IEEE, (2004)RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction., , and . ISCAS (4), page 4134-4137. IEEE, (2005)