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Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis., , , and . EDAC-ETC-EUROASIC, page 518-523. IEEE Computer Society, (1994)High Defect Coverage with Low-Power Test Sequences in a BIST Environment., , , , and . IEEE Des. Test Comput., 19 (5): 44-52 (2002)Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences., , , , and . J. Electron. Test., 17 (3-4): 233-241 (2001)A Gated Clock Scheme for Low Power Testing of Logic Cores., , , , , and . J. Electron. Test., 22 (1): 89-99 (2006)Generalized Distributed Comparison-Based System-Level Diagnosis., , , , , and . LATW, page 285-290. IEEE, (2001)Low power BIST design by hypergraph partitioning: methodology and architectures., , , and . ITC, page 652-661. IEEE Computer Society, (2000)An adjacency-based test pattern generator for low power BIST design., , , and . Asian Test Symposium, page 459-464. IEEE Computer Society, (2000)An optimized BIST test pattern generator for delay testing., , , and . VTS, page 94-100. IEEE Computer Society, (1997)A Test Vector Inhibiting Technique for Low Energy BIST Design., , , and . VTS, page 407-412. IEEE Computer Society, (1999)A Gated Clock Scheme for Low Power Scan-Based BIST., , , , and . IOLTW, page 87-89. IEEE Computer Society, (2001)