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Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering.

, and . DAC, page 361-366. ACM Press, (1993)

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Parallel logic simulation on a network of workstations using parallel virtual machine., , and . ACM Trans. Design Autom. Electr. Syst., 2 (2): 123-134 (1997)LILA: layout generation for iterative logic arrays., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (11): 1359-1369 (1995)Fault Tolerant Algorithms for Broadcasting on the Star Graph Network., , and . IEEE Trans. Computers, 46 (12): 1357-1362 (1997)Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering., and . DAC, page 361-366. ACM Press, (1993)Optimal cell generation for dual independent layout styles., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (6): 770-782 (1991)Transistor Chaining in Static CMOS Functional Cells of Arbitrary Planar Topology., , and . Discret. Appl. Math., 90 (1-3): 89-114 (1999)Principles vs. Practices in Undergraduate Microelectronic Systems Education.. MSE, page 22-23. IEEE Computer Society, (2001)Synthesis of SEU-tolerant ASICs using concurrent error correction., , and . Great Lakes Symposium on VLSI, page 90-93. IEEE Computer Society, (1995)Power estimation for a submicron CMOS inverter driving a CRC interconnect load., and . ACM Great Lakes Symposium on VLSI, page 162-166. ACM, (2000)A Unified Algorithm for the Estimation and Scheduling of Data Flow Graphs., and . Journal of Circuits, Systems, and Computers, 6 (3): 287-318 (1996)