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Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing., , , , and . ITC, page 1118-1127. IEEE Computer Society, (2004)An accurate functional level concurrent fault simulator., and . DAC, page 210-217. ACM/IEEE, (1980)Nand Flash Memory - Product Trends, Technology Overview, and Technical Challenges.. Asian Test Symposium, page 463. IEEE Computer Society, (2011)FACE Core Environment: The Model and Its Application in CAE/CAD Tool Development., , , , , , and . DAC, page 466-471. ACM Press, (1989)Flexible module generation in the FACE design environment., , , and . ICCAD, page 396-399. IEEE Computer Society, (1988)Concurrent Error Detection and Fault-Tolerance in Linear Digital State Variable Systems., and . FTCS, page 136-143. IEEE Computer Society, (1991)Panel: SoC power management implications on validation and testing., , , , , and . HLDVT, page 135-137. IEEE Computer Society, (2008)Controllability of Static CMOS Circuits for Timing Characterization., , , , and . J. Electron. Test., 24 (5): 481-496 (2008)A synthesis environment for designing DSP systems., , , , , , , and . IEEE Des. Test, 6 (2): 35-44 (1989)A Hierarchal Approach for Power Reduction in VLSI Chips., , and . Great Lakes Symposium on VLSI, page 182-. IEEE Computer Society, (1996)