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W neuromorphic chip optimized for deep learning and CMOS technology.

D. Miyashita, S. Kousai, T. Suzuki, and J. Deguchi. A-SSCC, page 25-28. IEEE, (2016)

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Chieko Miyashita

Daisuke Yoshida

Daisuke Shibata

Daisuke Akimoto

Naoko Miyashita

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A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems.Y. Tsubouchi, D. Miyashita, Y. Satoh, T. Toi, F. Tachibana, M. Morimoto, J. Wadatsumi, and J. Deguchi. VLSI Circuits, page 149-150. IEEE, (2018)Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision.K. Nakata, A. Maki, D. Miyashita, F. Tachibana, T. Suzuki, and J. Deguchi. ISCAS, page 1. IEEE, (2019)A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems.Y. Tsubouchi, D. Miyashita, T. Toi, Y. Satoh, F. Tachibana, J. Wadatsumi, M. Morimoto, R. Fujimoto, and J. Deguchi. IEEE J. Solid State Circuits, 54 (4): 1086-1095 (2019)Revisiting a kNN-Based Image Classification System with High-Capacity Storage.K. Nakata, Y. Ng, D. Miyashita, A. Maki, Y. Lin, and J. Deguchi. ECCV (37), volume 13697 of Lecture Notes in Computer Science, page 457-474. Springer, (2022)Convolutional neural networks using logarithmic data representationD. Miyashita, E. Lee, and B. Murmann. arXiv preprint arXiv:1603.01025, (2016)A 0.6V 380µW -14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner.J. Deguchi, D. Miyashita, and M. Hamada. ISSCC, page 224-225. IEEE, (2009)Can a Frozen Pretrained Language Model be used for Zero-shot Neural Retrieval on Entity-centric Questions?Y. Hoshi, D. Miyashita, Y. Morioka, Y. Ng, O. Torii, and J. Deguchi. CoRR, (2023)SimplyRetrieve: A Private and Lightweight Retrieval-Centric Generative AI Tool.Y. Ng, D. Miyashita, Y. Hoshi, Y. Morioka, O. Torii, T. Kodama, and J. Deguchi. CoRR, (2023)Adaptive Quantization Method for CNN with Computational-Complexity-Aware Regularization.K. Nakata, D. Miyashita, J. Deguchi, and R. Fujimoto. ISCAS, page 1-5. IEEE, (2021)3D-integrated, low-height, small module design techniques for 4.48GHz, 560MHz-bandwidth TransferJet™ transceiver.K. Agawa, I. Seto, A. Happoya, Y. Iida, Y. Imaizumi, M. Okano, D. Suzuki, Y. Sato, M. Iwanaga, K. Sato and 6 other author(s). RWS, page 76-78. IEEE, (2014)

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Disambiguation of "Miyashita, Daisuke"

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Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology.

Please choose a person to relate this publication to

Chieko Miyashita

Daisuke Yoshida

Daisuke Shibata

Daisuke Akimoto

Naoko Miyashita

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Miyashita, Daisuke"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology.

Please choose a person to relate this publication to

Chieko Miyashita

Daisuke Yoshida

Daisuke Shibata

Daisuke Akimoto

Naoko Miyashita

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology.