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Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation., , and . Microelectron. Reliab., 53 (6): 912-924 (2013)Soft error rate estimation for Combinational Logic in Presence of Single Event Multiple Transients., , and . Journal of Circuits, Systems, and Computers, (2014)Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology., , , and . Turkish J. Electr. Eng. Comput. Sci., (2017)Test data compression strategy while using hybrid-BIST methodology., , and . EWDTS, page 1-5. IEEE Computer Society, (2013)Multi-hop communications on wireless network-on-chip using optimized phased-array antennas., , , and . Comput. Electr. Eng., 39 (7): 2068-2085 (2013)Abnormal event detection and localisation in traffic videos based on group sparse topical coding., , and . IET Image Processing, 10 (3): 235-246 (2016)Single event upset immune latch circuit design using C-element., , and . ASICON, page 252-255. IEEE, (2011)Fast Causal Orientation Learning in Directed Acyclic Graphs., , and . CoRR, (2022)Compact and Secure Design of Masked AES S-Box., , , , and . ICICS, volume 4861 of Lecture Notes in Computer Science, page 216-229. Springer, (2007)Modeling traffic motion patterns via Non-negative Matrix Factorization., , , and . ICSIPA, page 214-219. IEEE, (2015)