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A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor.

A. Isobe, H. Tamura, K. Kato, T. Ohmaru, W. Uesugi, T. Ishizu, T. Onuki, K. Ohshima, T. Matsuzaki, A. Hirose, Y. Suzuki, N. Tsutsui, T. Atsumi, Y. Shionoiri, G. Goto, J. Koyama, M. Fujita, and S. Yamazaki. VLSIC, page 1-2. IEEE, (2014)

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The Fuce processor: The Execution Model and The Programming Methodologies.S. Amamiya, M. Izumi, T. Matsuzaki, and M. Amamiya. PDPTA, page 485-491. CSREA Press, (2006)A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor.A. Isobe, H. Tamura, K. Kato, T. Ohmaru, W. Uesugi, T. Ishizu, T. Onuki, K. Ohshima, T. Matsuzaki, A. Hirose and 8 other author(s). VLSIC, page 1-2. IEEE, (2014)Micro Short-Circuit Detector Including S/H Circuit for 1hr Retention and 52dB Comparator Composed of C-Axis Aligned Crystalline IGZO FETs for Li-Ion Battery Protection IC.H. Inoue, T. Aoki, F. Akasawa, T. Hamada, T. Takeuchi, K. Nei, T. Seki, Y. Yakubo, K. Takahashi, S. Fukai and 7 other author(s). ISSCC, page 204-206. IEEE, (2019)Soft- and Hard-Error Radiation Reliability of 228 KB $3T+1C$ Oxide Semiconductor Memory.H. Takahashi, Y. Okamoto, T. Hamada, Y. Komura, S. Watanabe, K. Tsuda, H. Sawai, T. Matsuzaki, Y. Ando, T. Onuki and 6 other author(s). IRPS, page 1-6. IEEE, (2023)UHF RFCPUs on Flexible and Glass Substrates for Secure RFID Systems.Y. Kurokawa, T. Ikeda, M. Endo, H. Dembo, D. Kawae, T. Inoue, M. Kozuma, D. Ohgarane, S. Saito, K. Dairiki and 9 other author(s). ISSCC, page 574-575. IEEE, (2007)Fuce: the continuation-based multithreading processor.S. Amamiya, M. Izumi, T. Matsuzaki, R. Hasegawa, and M. Amamiya. Conf. Computing Frontiers, page 213-224. ACM, (2007)An Architecture of Fusing Communication and Execution for Global Distributed Processing.M. Amamiya, H. Taniguchi, and T. Matsuzaki. Parallel Process. Lett., 11 (1): 7-24 (2001)Thread Control Mechanism for Multithreading Processor.T. Matsuzaki, N. Urashima, and M. Amamiya. CDES, page 81-87. CSREA Press, (2010)1Mbit 1T1C 3D DRAM with Monolithically Stacked One Planar FET and Two Vertical FET Heterogeneous Oxide Semiconductor layers over Si CMOS.Y. Okamoto, Y. Komura, T. Mizuguchi, T. Saito, M. Ito, K. Kimura, T. Onuki, Y. Ando, H. Sawai, T. Murakawa and 6 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)UHF RFCPUs on Flexible and Glass Substrates for Secure RFID Systems.Y. Kurokawa, T. Ikeda, M. Endo, H. Dembo, D. Kawae, T. Inoue, M. Kozuma, D. Ohgarane, S. Saito, K. Dairiki and 9 other author(s). IEEE J. Solid State Circuits, 43 (1): 292-299 (2008)

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor.

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