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Disambiguation of "Amano, Hideharu"

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Geyser-2: The second prototype CPU with fine-grained run-time power gating.

, , , , , , , , , , , , , , , , and . ASP-DAC, page 87-88. IEEE, (2011)

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Hideharu Umehara

Kyoko Amano

Yu Amano

Shun'ichi Amano

 

Other publications of authors with the same name

Adaptive Routing on the Recursive Diagonal Torus., , , and . ISHPC, volume 1336 of Lecture Notes in Computer Science, page 171-182. Springer, (1997)Performance evaluation of WASMII: a data driven computer on a virtual hardware., and . PARLE, volume 694 of Lecture Notes in Computer Science, page 610-621. Springer, (1993)3-D NoC on Inductive Wireless Interconnect., , , and . 3D Integration for NoC-based SoC Architectures, Springer, (2011)An LSI implementation of the simple serial synchronized multistage interconnection network., , and . ASP-DAC, page 673-674. IEEE, (1997)A prototype chip of multicontext FPGA with DRAM for virtual hardware., , and . ASP-DAC, page 17-18. ACM, (2001)Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays., , , , , , and . FPT, page 273-276. IEEE, (2007)The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator., , and . FPT, page 1-4. IEEE, (2011)A low power reconfigurable accelerator using a back-gate bias control technique., , , and . FPT, page 390-393. IEEE, (2013)A speculative gather system for Cool Mega-Array., , , , , and . FPT, page 346-349. IEEE, (2013)Variable pipeline structure for Coarse Grained Reconfigurable Array CMA., , , and . FPT, page 217-220. IEEE, (2016)