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Disambiguation of "Jr., Earl E. Swartzlander"

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Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS.

, , , , and . ASAP, page 335-343. IEEE Computer Society, (2002)

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Dent Earl

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Other publications of authors with the same name

VLSI Concurrent Error Correcting Adders and Multipliers., and . DFT, page 287-294. IEEE Computer Society, (1993)Parallel Counters.. IEEE Trans. Computers, 22 (11): 1021-1024 (1973)A Spanning Tree Carry Lookahead Adder., and . IEEE Trans. Computers, 41 (8): 931-939 (1992)A systolic array for 2-D DFT and 2-D DCT., and . ASAP, page 123-131. IEEE, (1994)Dadda Multiplier designs using memristors., and . ICICDT, page 1-4. IEEE, (2017)The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm., , and . VLSI-SoC (Selected Papers), volume 291 of IFIP, page 1-22. Springer, (2007)Estimating the power consumption of CMOS adders., and . IEEE Symposium on Computer Arithmetic, page 210-216. IEEE Computer Society/, (1993)A low-power dual-path floating-point fused add-subtract unit., , and . ACSCC, page 998-1002. IEEE, (2012)Modified non-restoring division algorithm with improved delay profile and error correction., and . ACSCC, page 1460-1464. IEEE, (2012)Memristor based adder circuit design., and . ACSSC, page 162-166. IEEE, (2016)