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An overview of the BlueGene/L Supercomputer.

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A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors., , , , , and . ISLPED, page 85-88. ACM, (2006)High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor., , , , , , and . VTS, page 234-238. IEEE Computer Society, (1998)Designing a Testable System on a Chip., , , , , , , , , and 5 other author(s). VTS, page 2-7. IEEE Computer Society, (1998)Alpha-particle-induced upsets in advanced CMOS circuits and technology., , , , , , and . IBM J. Res. Dev., 52 (3): 225-232 (2008)An on-chip jitter measurement circuit with sub-picosecond resolution., , and . ESSCIRC, page 157-160. IEEE, (2005)Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability., , , , and . CICC, page 519-522. IEEE, (1998)An overview of the BlueGene/L Supercomputer., , , , , , , , , and 105 other author(s). SC, page 7:1-7:22. IEEE Computer Society, (2002)Blue Gene/L, a System-On-A-Chip., , , , , , , , , and 55 other author(s). CLUSTER, page 349-. IEEE Computer Society, (2002)Single-Event-Upset Trends in Advanced CMOS Technologies.. DFT, IEEE Computer Society, (2006)Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability., , , , and . IEEE J. Solid State Circuits, 34 (8): 1108-1117 (1999)