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16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony.

, , , , , , , , , , and . ASP-DAC, page 49-. IEEE Computer Society, (1999)

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PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design., , and . ISCAS, page 31-34. IEEE, (1994)Hybrid ΣΔ modulators with adaptive calibration., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (5): 885-893 (2005)A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 52 (10): 2735-2745 (2017)A quadrature digital synthesizer/mixer architecture using fine/coarse coordinate rotation to achieve 14-b input, 15-b output, and 100-dBc SFDR., and . IEEE J. Solid State Circuits, 39 (11): 1853-1861 (2004)A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme., , and . IEEE J. Solid State Circuits, 32 (2): 289-291 (1997)Low-jitter digital timing recovery techniques for CAP-based VDSL applications., and . IEEE J. Solid State Circuits, 38 (10): 1649-1656 (2003)Non-Data-Aided Timing Recovery Algorithm for \pi/4-OPSK Modulated Signals., , , , and . ICC (1), page 392-396. IEEE, (2000)A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 36 (4): 648-657 (2001)A low-noise fast-lock phase-locked loop with adaptive bandwidth control., and . IEEE J. Solid State Circuits, 35 (8): 1137-1145 (2000)A DLL-Based Frequency Synthesizer with Selective Reuse of a Delay Cell Scheme for 2.4 GHz ISM Band., and . IEICE Trans. Electron., 88-C (1): 149-153 (2005)