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Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs., , , , , , , , , and 7 other author(s). IEEE Micro, 40 (4): 10-21 (2020)Invited: Chipyard - An Integrated SoC Research and Implementation Environment., , , , , , , , , and 8 other author(s). DAC, page 1-6. IEEE, (2020)A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance., , , , , , , , , and 21 other author(s). IEEE J. Solid State Circuits, 54 (10): 2786-2801 (2019)A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET., , , , , , , , , and . ESSCIRC, page 322-325. IEEE, (2018)Wireless Channel Dynamics for Relay Selection under Ultra-Reliable Low-Latency Communication., , , , , and . PIMRC, page 1-6. IEEE, (2020)A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET., , , , , , , , , and 21 other author(s). A-SSCC, page 285-288. IEEE, (2018)A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (7): 1993-2008 (2019)ACED: a hardware library for generating DSP systems., , , , , and . DAC, page 61:1-61:6. ACM, (2018)Wireless Channel Dynamics and Robustness for Ultra-Reliable Low-Latency Communications., , , , and . IEEE J. Sel. Areas Commun., 37 (4): 705-720 (2019)Performance of FORTRAN and C GPU Extensions for a Benchmark Suite of Fourier Pseudospectral Algorithms., , and . CoRR, (2012)