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Disambiguation of "Dehaene, Wim"

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Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (10): 1127-1135 (2005)

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Wim Lutzke

Wim Wätjen

Wim Broekaert

Wim Beyers

Wim Damen

 

Other publications of authors with the same name

Fully Integrated CMOS EME-Suppressing Current Regulator for Automotive Electronics., and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (2): 266-275 (2012)A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUs., and . IEEE J. Solid State Circuits, 52 (7): 1904-1914 (2017)Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor., and . IEEE J. Solid State Circuits, 57 (2): 651-660 (2022)Development of an Ultralow-Power Injection-Locked PSK Receiver Architecture., , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (1): 31-35 (2015)Transient Behavior and Phase Noise Performance of Pulsed-Harmonic Oscillators., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (7): 2119-2128 (2014)A high-voltage output driver in a 2.5-V 0.25-μm CMOS technology., , , and . IEEE J. Solid State Circuits, 40 (3): 576-583 (2005)A Thin-Film, a-IGZO, 128b SRAM and LPROM Matrix With Integrated Periphery on Flexible Foil., , , , , , , and . IEEE J. Solid State Circuits, 52 (11): 3095-3103 (2017)Ultra Low-Energy SRAM Design for Smart Ubiquitous Sensors., , , , , and . IEEE Micro, 32 (5): 10-24 (2012)A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh., , and . ESSCIRC, page 523-526. IEEE, (2011)Variation-resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency., and . ESSCIRC, page 474-477. IEEE, (2012)